Abstract: A testing device for checking a clock signal generated by a clock pulse generating circuit. The clock pulse generating circuit outputs a clock signal and a multiplied clock second signal. The testing device includes a reset circuit, a dividing unit and a mask circuit. The reset circuit receives a first reset signal and the clock signal and then generates a second reset signal synchronous with the clock signal. The second reset signal controls the dividing unit and the mask circuit. Inside the dividing unit, the multiplied clock signal is divided by an integral multiple to produce a divided clock signal. The divided clock signal is then passed to the mask circuit where uncertain portions of the third signal are blanketed to produce a masked clock signal. The masked clock signal is sent to a tester where cycle width of the masked clock signal is measured and first reset signal is sent to the reset circuit.