Abstract: The disclosure provides a control method of a moving body and a control system of a moving body, which allow a control part to calculate a fragment of a moving path between the moving body and a target according to position information of the moving body and the target, and transmit the fragment to the moving body. The above steps are repeatedly executed in sequence until the moving body reaches the target.

Abstract: A device, method and system for estimating elevation in images from camera devices is provided. The device detects humans at respective positions in images from a camera device, the camera device having a fixed orientation and fixed focal length. The device estimates, for the humans in the images, respective elevations of the humans, relative to the camera device, at the respective positions based at least on camera device parameters defining the fixed orientation and the fixed focal length. The device associates the respective elevations with the respective positions in the images. The device determines, using the respective elevations associated with the respective positions, a function that estimates elevation in an image from the camera device, using a respective image position coordinate as an input. The device provides the function to a video analytics engine to determine relative real-world positions in subsequent images from the camera device.

Abstract: A semiconductor device includes a substrate having a logic region and a high-voltage (HV) region, a first gate structure on the HV region, a first epitaxial layer and a second epitaxial layer adjacent to one side of the first gate structure, a first contact plug between the first epitaxial layer and the second epitaxial layer, a third epitaxial layer and a fourth epitaxial layer adjacent to another side of the first gate structure, and a second contact plug between the third epitaxial layer and the fourth epitaxial layer. Preferably, a bottom surface of the first epitaxial layer is lower than a bottom surface of the first contact plug and a bottom surface of the third epitaxial layer is lower than a bottom surface of the second contact plug.

Abstract: Provided are a memory cell and a method of forming the same. The memory cell includes a bottom electrode, a top electrode, a storage element layer, and a protective layer. The storage element layer is disposed between the bottom and top electrodes. The protective layer covers the storage element layer and the top electrode, and a material of the protective layer is derived from the storage element layer. A semiconductor device having the memory cell is also provided.

Abstract: An optical structure may be provided by forming a silicon grating structure over a dielectric material layer, depositing at least one dielectric material layer over the silicon grating structure, and depositing at least one dielectric etch stop layer over the at least one dielectric material layer. The at least one dielectric etch stop layer includes at least one dielectric material selected from silicon nitride and silicon oxynitride. A passivation dielectric layer may be formed over the at least one dielectric etch stop layer, and a patterned etch mask layer may be formed over the passivation dielectric layer. An opening may be formed through an unmasked portion of the passivation dielectric layer by performing an anisotropic etch process that etches the dielectric material selective to a silicon nitride or silicon oxynitride using the patterned etch mask layer as a masking structure. The at least one etch mask layer minimizes overetching.

Abstract: A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The package structure includes an outer lead portion, an inner lead portion, an encapsulant, and a first conductive layer. The outer lead portion has a first surface and a second surface opposite to the first surface. The inner lead portion is connected to the outer lead portion. The inner lead portion has a first surface and a second surface opposite to the first surface. The encapsulant covers the first surface of the outer lead portion and the first surface of the inner lead portion. The second surface of the outer lead portion and the second surface of the inner lead portion are substantially coplanar and are recessed from a surface of the encapsulant. The first conductive layer is disposed on the second surface of the outer lead portion.

Abstract: A semiconductor device includes a plurality of fins on a substrate, a fin end spacer plug on an end surface of each of the plurality of fins and a fin liner layer, an insulating layer on the plurality of fins, and a source/drain epitaxial layer in a source/drain recess in each of the plurality of fins.

Abstract: Provided are a memory cell and a method of forming the same. The memory cell includes a bottom electrode, an etching stop layer, a variable resistance layer, and a top electrode. The etching stop layer is disposed on the bottom electrode. The variable resistance layer is embedded in the etching stop layer and in contact with the bottom electrode. The top electrode is disposed on the variable resistance layer. A semiconductor device having the memory cell is also provided.

Abstract: A semiconductor device includes source and a drain above a substrate and spaced apart along a first direction, and a semiconductor channel extending between the source and the drain. The semiconductor device further includes gate spacers, an interfacial layer, and a metal gate structure. The gate spacers are disposed on the semiconductor channel and spaced apart by a spacer-to-spacer distance along the first direction. The interfacial layer is on the semiconductor channel. The interfacial layer extends a length along the first direction, and the length is less than a minimum of the spacer-to-spacer distance along the first direction. The metal gate structure is over the interfacial layer.

Abstract: A method for fabricating a photonic device is provided. The method includes forming an optical coupler and a waveguide structure connected to the optical coupler over a semiconductor substrate; forming a metal-dielectric stack over the optical coupler and the waveguide structure; etching a hole in the metal-dielectric stack and vertically overlapping the optical coupler; and forming a protection layer on a sidewall and a bottom of the hole.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first fin structure and a second fin structure formed over a substrate. The semiconductor device structure includes a first gate structure formed over the first fin structure, and the first gate structure includes a first portion of a gate dielectric layer and a first portion of a filling layer. The semiconductor device structure also includes a second gate structure formed over the second fin structure, and a first isolation sealing layer between the first gate structure and the second gate structure. The first isolation sealing layer is in direct contact with the first portion of the gate dielectric layer and the first portion of the filling layer.

Abstract: Provided is a memory device including a substrate, a stack structure on the substrate, a contact, and a supporting pillar. The stacked structure includes a plurality of conductive layers and a plurality of insulating layers stacked alternately on each other. The contact is connected to one of the plurality of conductive layers of the stack structure. The supporting pillar penetrates the stack structure and is disposed around the contact. The supporting pillar includes a body portion and a plurality of extension portions. The body portion is arranged around a first side of the contact. The plurality of extension portions are located on two sides of the body portion. A length of each of the extension portions is greater than a width of the contact, and one of the extension portions is disposed around a second side of the contact.

Abstract: A semiconductor device package includes a carrier, a semiconductor device, a lid, a conductive post, a first patterned conductive layer, a conductive element disposed between the first conductive post and the first patterned conductive layer, and an adhesive layer disposed between the lid and the carrier. The conductive post is electrically connected to the first patterned conductive layer. The semiconductor device is electrically connected to the first patterned conductive layer. The lid is disposed on the carrier, and the lid includes a second patterned conductive layer electrically connected to the first conductive post.

Abstract: The present disclosure provides transgenic plants and/or plant cells comprising overexpressed VirE2 gene or VirE2 protein in plant cytoplasm that upregulates or downregulates certain plant gene and/or proteins to facilitate transformation. The present disclosure further provides transgenic plants and/or plant cells comprising overexpressed plant gene or protein that upregulated by VirE2 gene or VirE2 protein for facilitating transformation. The transgenic plants and/or plant cells comprising downexpressed or knockout plant gene or protein that downregulated by VirE2 gene or VirE2 protein for facilitating transformation are also provided. Methods of making and using the transgenic plants and/or plants cells are also provided.

Abstract: A cross flow fan includes a fan frame and a rotor having a hub, a shaft connected with the hub at its rotation center, a plurality of blades, and a disk structure connected with the blades and hub within the fan frame. The fan frame has a frame wall having a lateral flow inlet to the rotor and a lateral flow outlet from the rotor, a base carrying the rotor and frame wall, a cover on one side of the frame wall opposite to the base, and a partition structure disposed between the blades and an inner wall surface of the frame wall. A normal line of the lateral flow inlet and a normal line of the lateral flow outlet are not parallel to an extension direction of the shaft. The blades directly face the lateral flow inlet and the lateral flow outlet along radial directions of the shaft.

Abstract: The present disclosure provides a series of mutant Agrobacterium strains generated by random mutagenesis of a wide-type or ? mutant VirD2 gene or VirD2 protein. The mutant Agrobacterium strains of the present disclosure transiently express T-DNA-encoded transgenes in a target plant but do not stably integrate these genes into the plant genome.

Abstract: The present invention relates to a structure analyzing method. The method includes dividing a physical structure into a plurality of virtual elements in accordance with a structural geometry of the physical structure and establishing a discrete increment secant iterative model including an equivalent nodal secant mass coefficient and an equivalent nodal secant mass damping coefficient; implementing an increment-secant iterative algorithm to repeatedly compute until convergence a secant mass coefficient slope corresponding to the equivalent nodal secant mass coefficient and a secant mass damping coefficient slope corresponding to the equivalent nodal secant mass damping coefficient; and replacing the equivalent nodal secant mass coefficient and the equivalent nodal secant mass damping coefficient by the converged secant mass coefficient slope and the converged secant mass damping coefficient slope respectively.

Abstract: A semiconductor structure and a manufacturing method for the same. The semiconductor structure includes a plug element and a via element. The plug element includes a tungsten plug. The plug element has a plug size in a lateral direction. The via element is electrically connected on the plug element. The via element is non-symmetrical with respect a center line of the plug element extending along a longitudinal direction. The via element has a via size in the lateral direction. The plug size is bigger than the via size.

Abstract: In a method for forming an integrated semiconductor device, a first transistor over is formed on a substrate; an inter-layer dielectric (ILD) layer is deposited over the first transistor; a gate conductive layer is deposited over the ILD layer; a gate dielectric layer is deposited over the gate conductive layer; the gate dielectric layer and the gate conductive layer are etched to form a gate stack; and a 2D material layer that has a first portion extending along a top surface and sidewalls of the gate stack and a second portion extending along a top surface of the ILD layer.

Abstract: A ball screw assembly includes a guider, an open nut, open shields, a first circulator, a second circulator, and ball circulating assemblies. The open nut is slidably fitted over the guider and includes an axial cylinder having an axial opening. Inner spiral channels of the axial cylinder and spiral channels of the guider form inner ball races. The open shields are coaxially fitted over the axial cylinder. An inner peripheral wall of each of the open shields and an outer annular wall of the axial cylinder form an outer ball race. The first circulator and the second circulator are disposed on the axial cylinder corresponding to the open shields. The inner ball races, first curves of the first circulator, the outer ball races, and second curves of the second circulator form ball circulating races, and the ball circulating assemblies roll in the ball circulating races.