Patents by Inventor Ying-Liang Chuang
Ying-Liang Chuang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240153826Abstract: Semiconductor devices and methods which utilize a treatment process of a bottom anti-reflective layer are provided. The treatment process may be a physical treatment process in which material is added in order to fill holes and pores within the material of the bottom anti-reflective layer or else the treatment process may be a chemical treatment process in which a chemical reaction is used to form a protective layer. By treating the bottom anti-reflective layer the diffusion of subsequently applied chemicals is reduced or eliminated, thereby helping to prevent defects that arise from such diffusion.Type: ApplicationFiled: January 11, 2024Publication date: May 9, 2024Inventors: Yao-Wen Hsu, Ming-Chi Huang, Ying-Liang Chuang
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Publication number: 20240096707Abstract: A method includes forming a gate stack, which includes a first portion over a portion of a first semiconductor fin, a second portion over a portion of a second semiconductor fin, and a third portion connecting the first portion to the second portion. An anisotropic etching is performed on the third portion of the gate stack to form an opening between the first portion and the second portion. A footing portion of the third portion remains after the anisotropic etching. The method further includes performing an isotropic etching to remove a metal gate portion of the footing portion, and filling the opening with a dielectric material.Type: ApplicationFiled: November 28, 2023Publication date: March 21, 2024Inventors: Ming-Chi Huang, Kuo-Bin Huang, Ying-Liang Chuang, Ming-Hsi Yeh
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Patent number: 11923201Abstract: Semiconductor device structures having metal gate structures with tunable work function values are provided. In one example, a first gate structure and a second gate structure formed on a substrate, wherein the first gate structure includes a first work function metal having a first material, and the second gate structure includes a second work function metal having a second material, the first material being different from the second material, wherein the first gate structure further includes a gate dielectric layer, a self-protective layer having metal phosphate, and the first work function metal on the self-protective layer.Type: GrantFiled: February 26, 2021Date of Patent: March 5, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ju-Li Huang, Ying-Liang Chuang, Ming-Hsi Yeh, Kuo-Bin Huang
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Patent number: 11923428Abstract: A semiconductor device includes a fin structure disposed over a substrate. The semiconductor device includes a first interfacial layer straddling the fin structure. The semiconductor device includes a gate dielectric layer extending along sidewalls of the fin structure. The semiconductor device includes a second interfacial layer overlaying a top surface of the fin structure. The semiconductor device includes a gate structure straddling the fin structure. The first interfacial layer and the gate dielectric layer are disposed between the sidewalls of the fin structure and the gate structure.Type: GrantFiled: April 20, 2023Date of Patent: March 5, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Chi Pan, Ying-Liang Chuang, Ming-Hsi Yeh, Kuo-Bin Huang
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Patent number: 11887896Abstract: Semiconductor devices and methods which utilize a treatment process of a bottom anti-reflective layer are provided. The treatment process may be a physical treatment process in which material is added in order to fill holes and pores within the material of the bottom anti-reflective layer or else the treatment process may be a chemical treatment process in which a chemical reaction is used to form a protective layer. By treating the bottom anti-reflective layer the diffusion of subsequently applied chemicals is reduced or eliminated, thereby helping to prevent defects that arise from such diffusion.Type: GrantFiled: June 13, 2022Date of Patent: January 30, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yao-Wen Hsu, Ming-Chi Huang, Ying-Liang Chuang
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Publication number: 20230420534Abstract: Disclosed is a semiconductor device and semiconductor fabrication method. A semiconductor device includes: a gate structure over a semiconductor substrate, having a low-k dielectric layer, a high-k dielectric layer, a p-type work function metal layer, an n-type work function metal layer, a silicon oxide scap layer, and a glue layer; and a continuous tungsten (W) cap over the gate structure that was formed by the gate structure being pretreated, W material being deposited and etched back, the scap layer being etched, additional W material being deposited, and unwanted W material being removed. A semiconductor fabrication method includes: receiving a gate structure; pretreating the gate structure; depositing W material on the gate structure; etching back the W material; etching the scap layer; depositing additional W material; and removing unwanted W material.Type: ApplicationFiled: January 12, 2023Publication date: December 28, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Ling Chung, Chun-Chih Cheng, Ying-Liang Chuang, Ming-Hsi Yeh, Kuo-Bin Huang
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Publication number: 20230420543Abstract: Disclosed is a semiconductor device and semiconductor fabrication method. A semiconductor device includes: a substrate having a metal gate, gate spacers on sides of the metal gate, an etch stop layer (ESL), and interlayer dielectric (ILD) material over a source/drain region; a tungsten (W) cap formed from W material deposited over the metal gate and between the gate spacers; and a via gate (VG) formed above the W cap. A semiconductor fabrication method includes: receiving a substrate having a metal gate, gate spacers on sides of the metal gate, an etch stop layer (ESL), and interlayer dielectric (ILD) material over a source/drain region; depositing tungsten (W) material over the substrate; removing unwanted W material to form a W cap; and forming a via gate (VG) on the W cap.Type: ApplicationFiled: June 27, 2022Publication date: December 28, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Ling Chung, Chun-Chih Cheng, Ying-Liang Chuang, Ming-Hsi Yeh, Kuo-Bin Huang
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Publication number: 20230420508Abstract: A method of forming a semiconductor device includes the following steps. A metal layer with at least one silicon-containing pattern therein is provided. A first wet etching process is performed by using a first etching solution, to clean a surface of the metal layer, wherein the first etching solution contains a base and a first oxidant. At least one cycle is performed. Each cycle includes a second wet etching process and a cleaning process. The second wet etching process is performed by using a second etching solution, to remove the metal layer, wherein the second etching solution contains an acid and a second oxidant. A cleaning process is performed.Type: ApplicationFiled: June 24, 2022Publication date: December 28, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Pei Yun Chung, Chun-Chih Cheng, Ying-Liang Chuang, Ming-Hsi Yeh, Kuo-Bin Huang
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Publication number: 20230420265Abstract: Disclosed is a method comprising: providing at least two structures with a metal layer over each; forming a patterned photolithographic layer over the metal layer over the first structure; removing the metal layer from the second structure via wet etch operations using a chemical etchant that is resistant to penetration into the photolithographic layer; and achieving, after wet etch operations, a remaining metal ratio of a distance X over a distance Y that is less than 179 and greater than 1, wherein X is the distance from a first line extending from an edge of the metal layer over the first structure to a second line extending from an edge of a channel region in the second structure, and Y is a second distance from the first line to a third line extending from an edge of the metal layer formed over the channel region in the first structure.Type: ApplicationFiled: June 22, 2022Publication date: December 28, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tefu Yeh, Cheng-Chieh Tu, Ming-Chi Huang, Ying-Liang Chuang, Ming-Hsi Yeh, Kuo-Bin Huang
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Patent number: 11854903Abstract: A method includes forming a gate stack, which includes a first portion over a portion of a first semiconductor fin, a second portion over a portion of a second semiconductor fin, and a third portion connecting the first portion to the second portion. An anisotropic etching is performed on the third portion of the gate stack to form an opening between the first portion and the second portion. A footing portion of the third portion remains after the anisotropic etching. The method further includes performing an isotropic etching to remove a metal gate portion of the footing portion, and filling the opening with a dielectric material.Type: GrantFiled: October 19, 2020Date of Patent: December 26, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Chi Huang, Kuo-Bin Huang, Ying-Liang Chuang, Ming-Hsi Yeh
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Patent number: 11854870Abstract: A method for making a middle-of-line interconnect structure in a semiconductor device includes forming, near a surface of a first interconnect structure comprised of a first metal, a region of varied composition including the first metal and a second element. The method further includes forming a recess within the region of varied composition. The recess laterally extends a first distance along the surface and vertically extends a second distance below the first surface. The method further includes filling the recess with a second metal to form a second interconnect structure that contacts the first interconnect structure.Type: GrantFiled: August 30, 2021Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chun-Cheng Chou, Yu-Fang Huang, Kuo-Ju Chen, Ying-Liang Chuang, Chun-Neng Lin, Ming-Hsi Yeh, Kuo-Bin Huang
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Publication number: 20230386898Abstract: A method for making a middle-of-line interconnect structure in a semiconductor device includes forming, near a surface of a first interconnect structure comprised of a first metal, a region of varied composition including the first metal and a second element. The method further includes forming a recess within the region of varied composition. The recess laterally extends a first distance along the surface and vertically extends a second distance below the first surface. The method further includes filling the recess with a second metal to form a second interconnect structure that contacts the first interconnect structure.Type: ApplicationFiled: August 9, 2023Publication date: November 30, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Cheng Chou, Yu-Fang Huang, Kuo-Ju Chen, Ying-Liang Chuang, Chun-Neng Lin, Ming-Hsi Yeh, Kuo-Bin Huang
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Publication number: 20230378360Abstract: The present disclosure describes structure and method of a fin field-effect transistor (finFET) device. The finFET device includes: a substrate, a fin over the substrate, and a gate structure over the fin. The gate structure includes a work-function metal (WFM) layer over an inner sidewall of the gate structure. A topmost surface of the WFM layer is lower than a top surface of the gate structure. The gate structure also includes a filler gate metal layer over the topmost surface of the WFM layer. A top surface of the filler gate metal layer is substantially co-planar with the top surface of the gate structure. The gate structure further includes a self-assembled monolayer (SAM) between the filler gate metal layer and the WFM layer.Type: ApplicationFiled: July 28, 2023Publication date: November 23, 2023Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ju-Li Huang, Hsin-Che Chiang, Yu-Chi Pan, Chun-Ming Yang, Chun-Sheng Liang, Ying-Liang Chuang, Ming-Hsi Yeh
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Publication number: 20230369063Abstract: A method for selectively removing a tungsten-including layer includes: forming a tungsten-including layer which has a first portion and a second portion; performing a treatment on a surface region of the first portion of the tungsten-including layer so as to convert tungsten in the surface region into tungsten oxide; and partially removing the tungsten-including layer using an etchant which has a higher etching selectivity to tungsten than tungsten oxide such that the second portion of the tungsten-including layer is fully removed, and the first portion of the tungsten-including layer, having the tungsten oxide in the surface region, is at least partially retained.Type: ApplicationFiled: May 12, 2022Publication date: November 16, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chia-Ling CHUNG, Chun-Chih CHENG, Ying-Liang CHUANG, Ming-Hsi YEH, Kuo-Bin HUANG
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Patent number: 11810978Abstract: The present disclosure describes structure and method of a fin field-effect transistor (finFET) device. The finFET device includes: a substrate, a fin over the substrate, and a gate structure over the fin. The gate structure includes a work-function metal (WFM) layer over an inner sidewall of the gate structure. A topmost surface of the WFM layer is lower than a top surface of the gate structure. The gate structure also includes a filler gate metal layer over the topmost surface of the WFM layer. A top surface of the filler gate metal layer is substantially co-planar with the top surface of the gate structure. The gate structure further includes a self-assembled monolayer (SAM) between the filler gate metal layer and the WFM layer.Type: GrantFiled: June 4, 2021Date of Patent: November 7, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ju-Li Huang, Hsin-Che Chiang, Yu-Chi Pan, Chun-Ming Yang, Chun-Sheng Liang, Ying-Liang Chuang, Ming-Hsi Yeh
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Publication number: 20230352346Abstract: A method for manufacturing a semiconductor device includes forming a metal-including layer over a semiconductor substrate; forming a hydrophobic polymer layer over the metal-including layer; and forming an amphiphilic polymer layer between the metal-including layer and the hydrophobic polymer layer so as to enhance a bonding force therebetween.Type: ApplicationFiled: April 27, 2022Publication date: November 2, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Li-Chen LEE, Ren-Kai CHEN, Ying-Liang CHUANG, Ming-Hsi YEH, Kuo-Bin HUANG
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Publication number: 20230343820Abstract: A method of forming a semiconductor device includes forming an epitaxial source/drain (S/D) structure adjacent to a gate structure; forming a dielectric structure over the gate and epitaxial S/D structures; forming a trench in the dielectric structure to accessibly expose a portion of the epitaxial S/D structure; forming a contact feature from the portion of the epitaxial S/D structure within the trench; and forming a S/D contact in the trench to be in contact with the contact feature overlying the epitaxial S/D structure. Forming the contact feature includes forming a metallic layer in the trench; performing a thermal process on the metallic layer to form the contact feature, where after the thermal process, metallic residues remain on a sidewall of a spacer of the dielectric structure in the trench; and removing the metallic residues by using a wet etching process, wherein the spacer of the dielectric structure remains substantially intact.Type: ApplicationFiled: April 21, 2022Publication date: October 26, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ren-Kai Chen, Li-Chen Lee, Ying-Liang Chuang, Ming-Hsi Yeh, Kuo-Bin Huang
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Publication number: 20230335443Abstract: A method includes depositing a first work function layer over a first and second gate trench. The method includes depositing a second work function layer over the first work function layer. The method includes etching the second work function layer in the first gate trench while covering the second work function layer in the second gate trench, causing the first work function layer in the first gate trench to contain metal dopants that are left from the second work function layer etched in the first gate trench. The method includes forming a first active gate structure and second active gate structure, which include the first work function layer and the metal dopants left from the second work function layer in the first gate trench, and the first work function layer and no metal dopants left behind from the second work function layer, respectively.Type: ApplicationFiled: June 20, 2023Publication date: October 19, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Chi Pan, Kuo-Bin Huang, Ming-Hsi Yeh, Ying-Liang Chuang, Yu-Te Su, Kuan-Wei Lin
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Publication number: 20230282699Abstract: A semiconductor device structure and a manufacturing method thereof are provided. The structure includes a substrate having a first region and a second region, first and second semiconductor channel sheets, first and second gate structure and source and drain regions. The first and second semiconductor channel sheets are disposed over the substrate and respectively in the first region and the second region. The first semiconductor channel sheets have a first channel width shorter than a second channel width of the second semiconductor channel sheets. The first and second gate structures are disposed over and laterally surrounding the first and second semiconductor channel sheets respectively. The first gate structure includes a first gate dielectric layer and a first metallic layer. The second gate structure includes a second gate dielectric layer and a second metallic layer. The source and drain regions are located beside the first and second semiconductor channel sheets.Type: ApplicationFiled: March 1, 2022Publication date: September 7, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tefu Yeh, Ming-Chi Huang, Jo-Chun Hung, Ying-Liang Chuang, Ming-Hsi Yeh, Kuo-Bin Huang
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Publication number: 20230253469Abstract: A semiconductor device includes a fin structure disposed over a substrate. The semiconductor device includes a first interfacial layer straddling the fin structure. The semiconductor device includes a gate dielectric layer extending along sidewalls of the fin structure. The semiconductor device includes a second interfacial layer overlaying a top surface of the fin structure. The semiconductor device includes a gate structure straddling the fin structure. The first interfacial layer and the gate dielectric layer are disposed between the sidewalls of the fin structure and the gate structure.Type: ApplicationFiled: April 20, 2023Publication date: August 10, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: YU-CHI PAN, Ying-Liang Chuang, Ming-Hsi Yeh, Kuo-Bin Huang