Patents by Inventor Ying Liao

Ying Liao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240303408
    Abstract: The application discloses a method and a system for shaping flexible blocks on a chip canvas in an integrated circuit design. An input is received describing geometric features of flexible blocks. A set of flexible blocks are generated based on the input. Obtained block areas of the set of flexible blocks are computed. Whether the set of flexible blocks are legal is determined based on determining whether area differences between the obtained block areas and a plurality of required areas for the set of flexible blocks meet a requirement. The set of flexible blocks are updated until the set of flexible blocks are all legal.
    Type: Application
    Filed: March 7, 2024
    Publication date: September 12, 2024
    Inventors: Kun-Yu WANG, Sheng-Tai TSENG, Yi-Ying LIAO, Jen-Wei LEE, Ronald Kuo-Hua HO, Bo-Jiun HSU, Te-Wei CHEN, Chun-Chih YANG, Tai-Lai TUNG
  • Patent number: 12041771
    Abstract: The present disclosure describes a patterning process for a strap region in a memory cell for the removal of material between polysilicon lines. The patterning process includes depositing a first hard mask layer in a divot formed on a top portion of a polysilicon layer interposed between a first polysilicon gate structure and a second polysilicon gate; depositing a second hard mask layer on the first hard mask layer. The patterning process also includes performing a first etch to remove the second hard mask layer and a portion of the second hard mask layer from the divot; performing a second etch to remove the second hard mask layer from the divot; and performing a third etch to remove the polysilicon layer not covered by the first and second hard mask layers to form a separation between the first polysilicon gate structure and the second polysilicon structure.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: July 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yen-Jou Wu, Chih-Ming Lee, Keng-Ying Liao, Ping-Pang Hsieh, Su-Yu Yeh, Hsin-Hui Lin, Yu-Liang Wang
  • Publication number: 20240213395
    Abstract: The present invention provides a manufacturing method of a light sensing element. The method includes the following steps: providing a preformed structure, wherein the preformed structure includes a semiconductor structure and a bandpass filter layer stacked on the semiconductor structure; performing a laser cutting process on the preformed structure along a direction perpendicular to a surface of the bandpass filter layer so that the preformed structure is cut into a plurality of light sensing elements. Each light sensing element has a plurality of sidewalls. Each sidewall forms a scorched surface by the laser cutting process to block the entry of external light.
    Type: Application
    Filed: December 26, 2023
    Publication date: June 27, 2024
    Inventors: Yang-Ting LIU, Keng-Ying LIAO, You-Hsien CHANG
  • Publication number: 20240136383
    Abstract: A semiconductor device includes a single-layered dielectric layer, a conductive line, a conductive via and a conductive pad. The conductive line and the conductive via are disposed in the single-layered dielectric layer. The conductive pad is extended into the single-layered dielectric layer to electrically connected to the conductive line.
    Type: Application
    Filed: January 3, 2024
    Publication date: April 25, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chien Ku, Huai-Jen Tung, Keng-Ying Liao, Yi-Hung Chen, Shih-Hsun Hsu, Yi-Fang Yang
  • Publication number: 20240136444
    Abstract: A flash memory device and method of making the same are disclosed. The flash memory device is located on a substrate and includes a floating gate electrode, a tunnel dielectric layer located between the substrate and the floating gate electrode, a smaller length control gate electrode and a control gate dielectric layer located between the floating gate electrode and the smaller length control gate electrode. The length of a major axis of the smaller length control gate electrode is less than a length of a major axis of the floating gate electrode.
    Type: Application
    Filed: December 22, 2023
    Publication date: April 25, 2024
    Inventors: Yu-Chu Lin, Chi-Chung Jen, Wen-Chih Chiang, Yi-Ling Liu, Huai-Jen Tung, Keng-Ying Liao
  • Patent number: 11903193
    Abstract: A MOSFET device and method of making, the device including a floating gate layer formed within a trench in a substrate, a tunnel dielectric layer located on sidewalls and a bottom of the trench, a control gate dielectric layer located on a top surface of the floating gate layer, a control gate layer located on a top surface of the control gate dielectric layer and sidewall spacers located on sidewalls of the control gate dielectric layer and the control gate layer.
    Type: Grant
    Filed: July 13, 2022
    Date of Patent: February 13, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chi-Chung Jen, Yu-Chu Lin, Y. C. Kuo, Wen-Chih Chiang, Keng-Ying Liao, Huai-Jen Tung
  • Patent number: 11901390
    Abstract: A semiconductor device includes a substrate, a dielectric layer, a plurality of dielectric patterns and a conductive pad. The substrate includes a first surface and a second surface opposite to the first surface. The dielectric layer is disposed at the first surface of the substrate, and the substrate is disposed between the dielectric layer and the second surface of the substrate. The dielectric patterns are disposed on the dielectric layer and between the first surface and the second surface of the substrate. The conductive pad is inserted between the plurality of dielectric patterns and extended into the dielectric layer.
    Type: Grant
    Filed: November 15, 2021
    Date of Patent: February 13, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chien Ku, Huai-Jen Tung, Keng-Ying Liao, Yi-Hung Chen, Shih-Hsun Hsu, Yi-Fang Yang
  • Publication number: 20240047496
    Abstract: An image sensor includes a substrate, a grid, and a color filter. The grid is over the substrate. From a cross-sectional view, the grid includes a first grid and a second grid over the first grid, the first grid has lower portion that has a first sidewall and a second sidewall opposing the first sidewall, the second grid has a third sidewall and a fourth sidewall opposing the third sidewall, and a width between the third sidewall and the fourth sidewall is less than a width between the first sidewall and the second sidewall. The color filter extends through the grid structure.
    Type: Application
    Filed: October 17, 2023
    Publication date: February 8, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chin-Yu LIN, Keng-Ying LIAO, Su-Yu YEH, Po-Zen CHEN, Huai-Jen TUNG, Hsien-Li CHEN
  • Patent number: 11888074
    Abstract: A flash memory device and method of making the same are disclosed. The flash memory device is located on a substrate and includes a floating gate electrode, a tunnel dielectric layer located between the substrate and the floating gate electrode, a smaller length control gate electrode and a control gate dielectric layer located between the floating gate electrode and the smaller length control gate electrode. The length of a major axis of the smaller length control gate electrode is less than a length of a major axis of the floating gate electrode.
    Type: Grant
    Filed: July 19, 2022
    Date of Patent: January 30, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yu-Chu Lin, Chi-Chung Jen, Yi-Ling Liu, Wen-Chih Chiang, Keng-Ying Liao, Huai-Jen Tung
  • Publication number: 20230389309
    Abstract: The present disclosure describes a patterning process for a strap region in a memory cell for the removal of material between polysilicon lines. The patterning process includes depositing a first hard mask layer in a divot formed on a top portion of a polysilicon layer interposed between a first polysilicon gate structure and a second polysilicon gate; depositing a second hard mask layer on the first hard mask layer. The patterning process also includes performing a first etch to remove the second hard mask layer and a portion of the second hard mask layer from the divot; performing a second etch to remove the second hard mask layer from the divot; and performing a third etch to remove the polysilicon layer not covered by the first and second hard mask layers to form a separation between the first polysilicon gate structure and the second polysilicon structure.
    Type: Application
    Filed: August 10, 2023
    Publication date: November 30, 2023
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yen-Jou WU, Hsin-Hui Lin, Yu-Liang Wang, Chih-Ming Lee, Keng-Ying Liao, Ping-Pang Hsieh, Su-Yu Yeh
  • Publication number: 20230376653
    Abstract: A neural network is used to place macros on a chip canvas in an integrated circuit (IC) design. The macros are first clustered into multiple macro clusters. Then the neural network generates a probability distribution over locations on a grid and aspect ratios of a macro cluster. The grid represents the chip canvas and is formed by rows and columns of grid cells. The macro cluster is described by at least an area size, aspect ratios, and wire connections. Action masks are generated for respective ones of the aspect ratios to block out a subset of unoccupied grid cells based on design rules that optimize macro placement. Then, by applying the action masks on the probability distribution, a masked probability distribution is generated. Based on the masked probability distribution, a location on the grid is selected for placing the macro cluster with a chosen aspect ratio.
    Type: Application
    Filed: May 11, 2023
    Publication date: November 23, 2023
    Inventors: Hsin-Chuan Kuo, Chia-Wei Chen, Yu-Hsiu Lin, Kun-Yu Wang, Sheng-Tai Tseng, Chun-Ku Ting, Fang-Ming Yang, Yu-Hsien Ku, Jen-Wei Lee, Ronald Kuo-Hua Ho, Chun-Chieh Wang, Yi-Ying Liao, Tai-Lai Tung, Ming-Fang Tsai, Chun-Chih Yang, Chih-Wei Ko, Kun-Chin Huang
  • Publication number: 20230376671
    Abstract: A neural network based method places flexible blocks on a chip canvas in an integrated circuit (IC) design. The neural network receives an input describing geometric features of a flexible block to be placed on the chip canvas. The geometric features includes an area size and multiple aspect ratios. The neural network generates a probability distribution over locations on the chip canvas and the aspect ratios of the flexible block. Based on the probability distribution, a location on the chip canvas is selected for placing the flexible block with a chosen aspect ratio.
    Type: Application
    Filed: May 11, 2023
    Publication date: November 23, 2023
    Inventors: Jen-Wei Lee, Yi-Ying Liao, Te-Wei Chen, Yu-Hsiu Lin, Chia-Wei Chen, Chun-Ku Ting, Sheng-Tai Tseng, Ronald Kuo-Hua Ho, Hsin-Chuan Kuo, Chun-Chieh Wang, Ming-Fang Tsai, Chun-Chih Yang, Tai-Lai Tung, Da-Shan Shiu
  • Publication number: 20230369430
    Abstract: A method includes sequentially depositing a floating gate layer, a dielectric structure stack, and a control gate layer over a substrate. A first etching process is performed to pattern the control gate layer, the dielectric structure stack, and a top portion of the floating gate layer to form a control gate, a dielectric structure, and a top portion of a floating gate over a bottom portion of the floating gate layer. A sidewall of the top portion of the floating gate is concave. A first spacer structure is formed on the sidewall of the top portion of the floating gate, a sidewall of the dielectric structure, and a sidewall of the control gate. A second etching process is performed to pattern the bottom portion of the floating gate layer to form a bottom portion of the floating gate after forming the first spacer structure.
    Type: Application
    Filed: July 25, 2023
    Publication date: November 16, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Chu LIN, Chi-Chung JEN, Chia-Ming PAN, Su-Yu YEH, Keng-Ying LIAO, Chih-Wei SUNG
  • Patent number: 11804529
    Abstract: A method includes depositing a gate dielectric film over a substrate. A floating gate layer and a control gate layer are deposited over the gate dielectric film. The control gate layer is patterned to form a control gate over the floating gate layer. A top portion of the floating gate layer is patterned. A spacer structure is formed on a sidewall of the control gate and over a remaining portion of the floating gate layer. The remaining portion of the floating gate layer is patterned to form a bottom portion of a floating gate. A ratio of the bottom width of the bottom portion to the middle width of the bottom portion is in a range between about 103% and about 108%. The gate dielectric film is patterned form a gate dielectric layer.
    Type: Grant
    Filed: March 18, 2022
    Date of Patent: October 31, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Chu Lin, Chi-Chung Jen, Chia-Ming Pan, Su-Yu Yeh, Keng-Ying Liao, Chih-Wei Sung
  • Publication number: 20230342889
    Abstract: Systems, methods, and non-transitory media are provided for frequency domain edge enhancement of multi-exposure high dynamic range (HDR) images. An example method can include determining an alignment between an HDR frame and a frame having an exposure time above a threshold; adjusting the frame based on the alignment; determining a gradient estimation map representing differences between image blocks in the HDR frame and image blocks in the frame; and generating, based on the gradient estimation map, a merged frame that includes a combination of at least some image data from the HDR frame and at least some image data from the frame.
    Type: Application
    Filed: April 26, 2022
    Publication date: October 26, 2023
    Inventors: Wen-Chun FENG, Hsuan-Ying LIAO, Hsin Yueh CHANG, Yu-Ren LAI, Shizhong LIU, Weiliang LIU
  • Publication number: 20230343844
    Abstract: A flash memory device includes a floating gate electrode formed within a substrate semiconductor layer having a doping of a first conductivity type, a pair of active regions formed within the substrate semiconductor layer, having a doping of a second conductivity type, and laterally spaced apart by the floating gate electrode, an erase gate electrode formed within the substrate semiconductor layer and laterally offset from the floating gate electrode, and a control gate electrode that overlies the floating gate electrode. The floating gate electrode may be formed in a first opening in the substrate semiconductor layer, and the erase gate electrode may be formed in a second opening in the substrate semiconductor layer. Multiple instances of the flash memory device may be arranged as a two-dimensional array of flash memory cells.
    Type: Application
    Filed: June 19, 2023
    Publication date: October 26, 2023
    Inventors: Yu-Chu Lin, Chia-Ming Pan, Chi-Chung Jen, Wen-Chih Chiang, Huai-Jen Tung, Keng-Ying Liao
  • Patent number: 11792981
    Abstract: A MOSFET device and method of making, the device including a floating gate layer formed within a trench in a substrate, a tunnel dielectric layer located on sidewalls and a bottom of the trench, a control gate dielectric layer located on a top surface of the floating gate layer, a control gate layer located on a top surface of the control gate dielectric layer and sidewall spacers located on sidewalls of the control gate dielectric layer and the control gate layer.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: October 17, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chi-Chung Jen, Yu-Chu Lin, Y. C. Kuo, Wen-Chih Chiang, Keng-Ying Liao, Huai-Jen Tung
  • Patent number: 11728399
    Abstract: A flash memory device includes a floating gate electrode formed within a substrate semiconductor layer having a doping of a first conductivity type, a pair of active regions formed within the substrate semiconductor layer, having a doping of a second conductivity type, and laterally spaced apart by the floating gate electrode, an erase gate electrode formed within the substrate semiconductor layer and laterally offset from the floating gate electrode, and a control gate electrode that overlies the floating gate electrode. The floating gate electrode may be formed in a first opening in the substrate semiconductor layer, and the erase gate electrode may be formed in a second opening in the substrate semiconductor layer. Multiple instances of the flash memory device may be arranged as a two-dimensional array of flash memory cells.
    Type: Grant
    Filed: October 8, 2021
    Date of Patent: August 15, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yu-Chu Lin, Chia-Ming Pan, Chi-Chung Jen, Wen-Chih Chiang, Keng-Ying Liao, Huai-jen Tung
  • Publication number: 20230253508
    Abstract: A flash memory device and method of making the same are disclosed. The flash memory device is located on a substrate and includes a floating gate electrode, a tunnel dielectric layer located between the substrate and the floating gate electrode, a smaller length control gate electrode and a control gate dielectric layer located between the floating gate electrode and the smaller length control gate electrode. The length of a major axis of the smaller length control gate electrode is less than a length of a major axis of the floating gate electrode.
    Type: Application
    Filed: April 15, 2023
    Publication date: August 10, 2023
    Inventors: Yu-Chu LIN, Chi-Chung JEN, Wen-Chih CHIANG, Yi-Ling LIU, Huai-jen TUNG, Keng-Ying LIAO
  • Publication number: 20230253433
    Abstract: A device is disclosed. The device includes a plurality of pixels disposed over a first surface of a semiconductor layer. The device includes a device layer disposed over the first surface. The device includes metallization layers disposed over the device layer. One of the metallization layers, closer to the first surface than any of other ones of the metallization layers, includes at least one conductive structure. The device includes an oxide layer disposed over a second surface of the semiconductor layer, the second surface being opposite to the first surface, the oxide layer also lining a recess that extends through the semiconductor layer. The device includes a spacer layer disposed between inner sidewalls of the recess and the oxide layer. The device includes a pad structure extending through the oxide layer and the device layer to be in physical contact with the at least one conductive structure.
    Type: Application
    Filed: April 17, 2023
    Publication date: August 10, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Keng-Ying Liao, Yu-Chu Lin, Chih Wei Sung, Shih Sian Wang, Chi-Chung Jen, Yu-chien Ku, Yen-Jou Wu, Huai-jen Tung, Po-Zen Chen