Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a spacer adjacent to the MTJ, a liner adjacent to the spacer, and a first metal interconnection on the MTJ. Preferably, the first metal interconnection includes protrusions adjacent to two sides of the MTJ and a bottom surface of the protrusions contact the liner directly.

Abstract: A method including providing a device including a gate structure and a source/drain feature adjacent to the gate structure. An insulating layer (e.g., CESL, ILD) is formed over the source/drain feature. A trench is etched in the insulating layer to expose a surface of the source/drain feature. A semiconductor material is then formed in the etched trench on the surface of the source/drain feature. The semiconductor material is converted to a silicide.

Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on one side of the of the MTJ, a second spacer on another side of the MTJ, a first metal interconnection on the MTJ, and a liner adjacent to the first spacer, the second spacer, and the first metal interconnection. Preferably, each of a top surface of the MTJ and a bottom surface of the first metal interconnection includes a planar surface and two sidewalls of the first metal interconnection are aligned with two sidewalls of the MTJ.

Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on one side of the of the MTJ, a second spacer on another side of the MTJ, a first metal interconnection on the MTJ, and a liner adjacent to the first spacer, the second spacer, and the first metal interconnection. Preferably, each of a top surface of the MTJ and a bottom surface of the first metal interconnection includes a planar surface and two sidewalls of the first metal interconnection are aligned with two sidewalls of the MTJ.

Abstract: Methods, compositions, kits and apparatuses that include a fluid, the fluid containing a ternary complex and Li+, wherein the ternary complex includes a primed template nucleic acid, a polymerase, and a nucleotide cognate for the next correct base for the primed template nucleic acid molecule. As an alternative or addition to Li+, the fluid can contain betaine or a metal ion that inhibits polymerase catalysis such as Ca2+. In addition to Li+, the fluid can contain polyethylenimine (PEI) with or without betaine.

Abstract: Methods, compositions, kits and apparatuses that include a fluid, the fluid containing a ternary complex and Li+, wherein the ternary complex includes a primed template nucleic acid, a polymerase, and a nucleotide cognate for the next correct base for the primed template nucleic acid molecule. As an alternative or addition to Li+, the fluid can contain betaine or a metal ion that inhibits polymerase catalysis such as Ca2+. In addition to Li+, the fluid can contain polyethylenimine (PEI) with or without betaine.

Abstract: Methods, compositions, kits and apparatuses that include a fluid, the fluid containing a ternary complex and Li+, wherein the ternary complex includes a primed template nucleic acid, a polymerase, and a nucleotide cognate for the next correct base for the primed template nucleic acid molecule. As an alternative or addition to Li+, the fluid can contain betaine or a metal ion that inhibits polymerase catalysis such as Ca2+. In addition to Li+, the fluid can contain polyethylenimine (PEI) with or without betaine.

Abstract: Methods, compositions, kits and apparatuses that include a fluid, the fluid containing a ternary complex and Li+, wherein the ternary complex includes a primed template nucleic acid, a polymerase, and a nucleotide cognate for the next correct base for the primed template nucleic acid molecule. As an alternative or addition to Li+, the fluid can contain betaine or a metal ion that inhibits polymerase catalysis such as Ca2+. In addition to Li+, the fluid can contain polyethylenimine (PEI) with or without betaine.

Abstract: A method of designing and verifying 3D integrated circuits (3D IC) including providing a first layout corresponding to a first device of a 3D IC. The first layout includes a first interface layer. A second layout corresponding to a second device of the 3D IC is also provided. The second layout includes a second interface layer. A verification of the 3D is performed by verifying the first and second interface layers. The verification includes performing at least one of a design rule check (DRC) or a layout-versus-schematic (LVS) on the first and/or second interface layers.

Abstract: A method of designing and verifying 3D integrated circuits (3D IC) including providing a first layout corresponding to a first device of a 3D IC. The first layout includes a first interface layer. A second layout corresponding to a second device of the 3D IC is also provided. The second layout includes a second interface layer. A verification of the 3D is performed by verifying the first and second interface layers. The verification includes performing at least one of a design rule check (DRC) or a layout-versus-schematic (LVS) on the first and/or second interface layers.

Abstract: A method of designing a 3D integrated circuit (3D IC) including providing a first layout corresponding to a first device of a 3D IC and a second layout corresponding to a second device of a 3D IC is provided. A verification, such as LVS or DRC, may be performed not only on each device separately, but may also be performed to ensure proper connectivity between devices. The verification may be performed on a single layout file (e.g., GDS II file) including the interface layer of the first and second die. Dummy feature pattern may be determined for the 3D IC using a layout including the interface layers of the first and second devices.

Abstract: A method of designing a 3D integrated circuit (3D IC) including providing a first layout corresponding to a first device of a 3D IC and a second layout corresponding to a second device of a 3D IC is provided. A verification, such as LVS or DRC, may be performed not only on each device separately, but may also be performed to ensure proper connectivity between devices. The verification may be performed on a single layout file (e.g., GDS II file) including the interface layer of the first and second die. Dummy feature pattern may be determined for the 3D IC using a layout including the interface layers of the first and second devices.