Patents by Inventor Ying LONG

Ying LONG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11673196
    Abstract: A method to achieve full densification and grain size control for sintering metal materials, wherein raw material powder is deagglomerated to obtain deagglomerated powder with dispersion. The deagglomerated powder is granulated by spray granulation. The granulated particles are processed by high-pressure die pressing and cold isostatic pressing. The powder compact is sintered by two-step pressureless sintering. The first step is to heat up the powder compact to a higher temperature and hold for a short time to obtain 75-85% theoretical density; the second step is to cool down powder compact to a lower temperature and hold for a long time. The two-step sintering can decrease the sintering temperature, so that the powder compact can be densified at a lower temperature. Thus, the obtained refractory metal product is densified, with ultrafine grains, uniform grain size distribution, and outstanding mechanical properties.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: June 13, 2023
    Assignee: UNIVERSITY OF SCIENCE AND TECHNOLOGY BEIJING
    Inventors: Lin Zhang, Xuanhui Qu, Xingyu Li, Mingli Qin, Yanhao Dong, Ju Li, Guanghua Wang, Ying Long, Wei Zhong
  • Patent number: 10706332
    Abstract: An analog circuit fault mode classification method comprises the following implementation steps: (1) collecting M groups of voltage signal sample vectors Vij to each of fault modes Fi of the analog circuit by using a data collection board; (2) sequentially extracting fault characteristic vectors VijF of the voltage signal sample vectors Vij by using subspace projection; (3) standardizing the extracted fault characteristic vectors VijF to obtain standardized fault characteristic vectors; (4) constructing a fault mode classifier based on a support vector machine, inputting the standardized fault characteristic vectors, performing learning and training on the classifier, and determining structure parameters of the classifier; and (5) completing determination of fault modes according to fault mode determination rules. The fault mode classifier of the present invention is simple in learning and training and reliable in mode classification accuracy.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: July 7, 2020
    Assignee: HEFEI UNIVERSITY OF TECHNOLOGY
    Inventors: Lifen Yuan, Shuai Luo, Yigang He, Peng Chen, Chaolong Zhang, Ying Long, Zhen Cheng, Zhijie Yuan, Deqin Zhao
  • Publication number: 20200198013
    Abstract: The present invention provides a method to achieve full densification and grain size control for sintering metal materials. First, raw material powder is deagglomerated to obtain deagglomerated powder with dispersion. The deagglomerated powder is granulated by spray granulation. The granulated particles are processed by high-pressure die pressing and cold isostatic pressing. The powder compact is sintered by two-step pressureless sintering. The first step is to heat up the powder compact to a higher temperature and hold for a short time to obtain 75-85% theoretical density; the second step is to cool down powder compact to a lower temperature and hold for a long time. The two-step sintering can decrease the sintering temperature, so that the powder compact can be densified at a lower temperature. Thus, the obtained refractory metal product is densified, with ultrafine grains, uniform grain size distribution, and outstanding mechanical properties.
    Type: Application
    Filed: February 18, 2020
    Publication date: June 25, 2020
    Inventors: Lin ZHANG, Xuanhui QU, Xingyu LI, Mingli QIN, Yanhao DONG, Ju LI, Guanghua WANG, Ying LONG, Wei ZHONG
  • Patent number: 10539613
    Abstract: An analog circuit fault diagnosis method using a single testable node comprises the following steps: (1) obtaining prior sample data vectors under each fault mode; (2) computing a statistical average of the prior sample data vectors under each of the fault modes; (3) decomposing a signal by an orthogonal Haar wavelet filter set; (4) extracting the feature factor of the prior sample fault modes; (5) extracting a fault-mode-to-be-tested feature factor; (6) computing a correlation coefficient matrix and correlation metric parameters between the feature factor of the prior sample fault modes and the feature factor of the fault-mode-to-be-tested; and (7) determining a fault mode according to a maximal correlation principle by comparing the correlation metric parameters.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: January 21, 2020
    Assignee: HEFEI UNIVERSITY OF TECHNOLOGY
    Inventors: Yigang He, Lifen Yuan, Lei Wu, Yesheng Sun, Chaolong Zhang, Ying Long, Zhen Cheng, Zhijie Yuan, Deqin Zhao
  • Publication number: 20180039865
    Abstract: An analog circuit fault mode classification method comprises the following implementation steps: (1) collecting M groups of voltage signal sample vectors Vij to each of fault modes Fi of the analog circuit by using a data collection board; (2) sequentially extracting fault characteristic vectors VijF of the voltage signal sample vectors Vij by using subspace projection; (3) standardizing the extracted fault characteristic vectors VijF to obtain standardized fault characteristic vectors; (4) constructing a fault mode classifier based on a support vector machine, inputting the standardized fault characteristic vectors, performing learning and training on the classifier, and determining structure parameters of the classifier; and (5) completing determination of fault modes according to fault mode determination rules. The fault mode classifier of the present invention is simple in learning and training and reliable in mode classification accuracy.
    Type: Application
    Filed: November 24, 2015
    Publication date: February 8, 2018
    Applicant: HEFEI UNIVERSITY OF TECHNOLOGY
    Inventors: Lifen YUAN, Shuai LUO, Yigang HE, Peng CHEN, Chaolong ZHANG, Ying LONG, Zhen CHENG, Zhijie YUAN, Deqin ZHAO
  • Publication number: 20180038909
    Abstract: An analog circuit fault diagnosis method using a single testable node comprises the following steps: (1) obtaining prior sample data vectors under each fault mode; (2) computing a statistical average of the prior sample data vectors under each of the fault modes; (3) decomposing a signal by an orthogonal Haar wavelet filter set; (4) extracting the feature factor of the prior sample fault modes; (5) extracting a fault-mode-to-be-tested feature factor; (6) computing a correlation coefficient matrix and correlation metric parameters between the feature factor of the prior sample fault modes and the feature factor of the fault-mode-to-be-tested; and (7) detennining a fault mode according to a maximal correlation principle by comparing the correlation metric parameters.
    Type: Application
    Filed: November 25, 2015
    Publication date: February 8, 2018
    Applicant: HEFEI UNIVERSITY OF TECHNOLOGY
    Inventors: Yigang HE, Lifen YUAN, Lei WU, Yesheng SUN, Chaolong ZHANG, Ying LONG, Zhen CHENG, Zhijie YUAN, Deqin ZHAO
  • Patent number: 9290847
    Abstract: The present invention provides an Al2O3 coated Si3N4 cutting tool comprising a Si3N4 based substrate body and a coating layer on the substrate body, wherein the coating layer has at least one Al2O3 coating layer consisting of amorphous Al2O3 or nanocrystalline ?-, ?-, or ?-Al2O3. The hard and wear resistant refractory coating is deposited onto the Si3N4-based substrate body by reactive sputtering using bipolar pulsed DMS technique or dual magnetron sputtering method at substrate temperatures of 300-700° C. During the deposition, preferably, the substrate temperature is controlled to achieve the desired crystal structure of the coating. To form amorphous Al2O3 coating on the surface of the substrates, the deposition temperature can be controlled from 300 to 500° C.; on the other hand, to form nanocrystalline ?-, ?-, or ?-Al2O3, the deposition temperature can be controlled in the range of 500-700° C.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: March 22, 2016
    Assignee: GUANGDONG UNIVERSITY OF TECHNOLOGY
    Inventors: Shanghua Wu, Ying Long, Qimin Wang, Chengyong Wang
  • Publication number: 20140178659
    Abstract: The present invention provides an Al2O3 coated Si3N4 cutting tool comprising a Si3N4 based substrate body and a coating layer on the substrate body, wherein the coating layer has at least one Al2O3 coating layer consisting of amorphous Al2O3 or nanocrystalline ?-, ?-, or ?-Al2O3. The hard and wear resistant refractory coating is deposited onto the Si3N4-based substrate body by reactive sputtering using bipolar pulsed DMS technique or dual magnetron sputtering method at substrate temperatures of 300-700° C. During the deposition, preferably, the substrate temperature is controlled to achieve the desired crystal structure of the coating. To form amorphous Al2O3 coating on the surface of the substrates, the deposition temperature can be controlled from 300 to 500° C.; on the other hand, to form nanocrystalline ?-, ?-, or ?-Al2O3, the deposition temperature can be controlled in the range of 500-700° C.
    Type: Application
    Filed: December 23, 2013
    Publication date: June 26, 2014
    Inventors: Shanghua WU, Ying LONG, Qimin WANG, Chengyong WANG