Patents by Inventor Ying Min CHOU
Ying Min CHOU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10134896Abstract: A semiconductor substructure with an improved source/drain structure is described. The semiconductor substructure can include an upper surface; a gate structure formed over the substrate; a spacer formed along a sidewall of the gate structure; and a source/drain structure disposed adjacent the gate structure. The source/drain structure is disposed over or on a recess surface of a recess that extends below said upper surface. The source/drain structure includes a first epitaxial layer, having a first composition, over or on the interface surface, and a subsequent epitaxial layer, having a subsequent composition, over or on the first epitaxial layer. A dopant concentration of the subsequent composition is greater than a dopant concentration of the first composition, and a carbon concentration of the first composition ranges from 0 to 1.4 at.-%. Methods of making semiconductor substructures including improved source/drain structures are also described.Type: GrantFiled: March 1, 2013Date of Patent: November 20, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chun Hsiung Tsai, Sheng-Wen Yu, Ying-Min Chou, Yi-Fang Pai
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Patent number: 9735271Abstract: A semiconductor device includes an isolation feature in a substrate. The semiconductor device further includes a first source/drain feature in the substrate, wherein a first side of the first source/drain feature contacts the isolation feature, and the first source/drain feature exposes a portion of the isolation feature below a top surface of the substrate. The semiconductor device further includes a silicide layer over the first source/drain feature. The semiconductor device further includes a dielectric layer along the exposed portion of the isolation feature below the top surface of the substrate, wherein the dielectric layer contacts the silicide layer. The semiconductor device further includes a second source/drain feature in the substrate on an opposite side of a gate stack from the first source/drain feature, wherein the second source/drain feature has a substantially uniform thickness.Type: GrantFiled: March 2, 2016Date of Patent: August 15, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wen Chu Hsiao, Lai Wan Chong, Chun-Chieh Wang, Ying Min Chou, Hsiang Hsiang Ko, Ying-Lang Wang
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Surface tension modification using silane with hydrophobic functional group for thin film deposition
Patent number: 9698263Abstract: A semiconductor structure that includes crystalline surfaces and amorphous hydrophilic surfaces is provided. The hydrophilic surfaces are treated with silane that includes a hydrophobic functional group, converting the hydrophilic surfaces to hydrophobic surfaces. Chemical vapor deposition or other suitable deposition methods are used to simultaneously deposit a material on both surfaces and due to the surface treatment, the deposited material exhibits superior adherence qualities on both surfaces. In one embodiment, the structure is an opening formed in a semiconductor substrate and bounded by at least one portion of a crystalline silicon surface and at least one portion of an amorphous silicon oxide structure.Type: GrantFiled: November 19, 2015Date of Patent: July 4, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Lai-Wan Chong, Wen-Chu Hsiao, Ying-Min Chou, Hsiang-Hsiang Ko -
Patent number: 9634119Abstract: A method includes providing a gate structure over a semiconductor substrate and forming a source/drain region associated with the gate structure by etching an opening in the semiconductor substrate, performing a first epitaxial growth process while an entirety of a sidewall of the opening is exposed to grow a first epitaxy material in the opening. The first epitaxial growth process is free of a first dopant impurity. A second epitaxial growth process is performed after first epitaxial growth process to grow a second epitaxy material on the first epitaxy material. The second epitaxy material has the first dopant impurity at a first concentration. Further, a third epitaxial growth process is performed after the second epitaxial growth process that includes introducing the first dopant impurity at a second concentration, the second concentration greater than the first concentration.Type: GrantFiled: June 19, 2015Date of Patent: April 25, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen Chu Hsiao, Ju Wen Hsiao, Ying Min Chou, Hsiang Hsiang Ko, Ying-Lang Wang
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Patent number: 9564513Abstract: A semiconductor structure including a semiconductor substrate is provided. The semiconductor substrate includes a surface. A gate structure is provided on the surface. An interface lower than the surface is provided. An epitaxial regrowth region adjacent the gate structure is disposed on the interface. In addition, the epitaxial regrowth region extends over the surface and includes a bottom layer and a cap layer. The activation of the cap layer is lower than that of the bottom layer. Moreover, the bottom layer is lower than the surface and the gate structure. Furthermore, the bottom layer includes a first downwardly-curved edge and a second downwardly-curved edge over the first one. The first downwardly-curved edge is connected with the second downwardly-curved edge at two endpoints. The two endpoints are in contact with the surface of the semiconductor substrate.Type: GrantFiled: February 14, 2014Date of Patent: February 7, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Shih-Chieh Chang, Ying-Min Chou, Yi-Ming Huang, Chun-Ju Huang, Huai-Tei Yang, Kei-Wei Chen
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Patent number: 9553191Abstract: A method of fabricating a FinFET includes at last the following steps. A semiconductor substrate is patterned to form a plurality of trenches in the semiconductor substrate and at least one semiconductor fin between the trenches. Insulators are formed in the trenches. A gate stack is formed over portions of the semiconductor fin and over portions of the insulators. A strained material doped with a conductive dopant is formed over portions of the semiconductor fin revealed by the gate stack, and the strained material is formed by selectively growing a bulk layer with a gradient doping concentration.Type: GrantFiled: November 16, 2015Date of Patent: January 24, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chin-I Liao, Mon-Nan How, Shih-Chieh Chang, Ying-Min Chou, Ting-Chang Chang
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Patent number: 9543387Abstract: A semiconductor device includes a gate structure located on a substrate and a raised source/drain region adjacent to the gate structure. The raised source/drain region includes: a first epitaxial-grown doped layer of the raised source/drain region in contact with the substrate; a second epitaxial-grown doped layer on the first epitaxial-grown doped layer and including a same dopant species as the first epitaxial-grown doped layer, wherein the second epitaxial-grown doped layer includes a higher dopant concentration than the first epitaxial-grown doped layer and interfacing the gate structure by using a predetermined distance; and a third epitaxial-grown doped layer on the second epitaxial-grown doped layer and including the same dopant species as the first epitaxial-grown doped layer, wherein the third epitaxial-grown doped layer includes a higher dopant concentration than the second epitaxial-grown doped layer.Type: GrantFiled: March 10, 2014Date of Patent: January 10, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Shih-Chieh Chang, Ying-Min Chou, Yi-Ming Huang, Wen-Chu Hsiao, Hsiu-Ting Chen, Huai-Tei Yang
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Patent number: 9406797Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes proving a substrate. The substrate includes a gate stack over the substrate and source/drain regions separated by the gate stack. A first dislocation with a first pinch-off point is formed within the source/drain region with a first depth. A second dislocation with a second pinch-off point is formed within the source/drain region at a second depth. The second depth is substantial smaller than the first depth.Type: GrantFiled: March 7, 2014Date of Patent: August 2, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shiu-Ko JangJian, Chun-Chieh Wang, Shih-Chieh Chang, Ying-Min Chou
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SURFACE TENSION MODIFICATION USING SILANE WITH HYDROPHOBIC FUNCTIONAL GROUP FOR THIN FILM DEPOSITION
Publication number: 20160190320Abstract: A semiconductor structure that includes crystalline surfaces and amorphous hydrophilic surfaces is provided. The hydrophilic surfaces are treated with silane that includes a hydrophobic functional group, converting the hydrophilic surfaces to hydrophobic surfaces. Chemical vapor deposition or other suitable deposition methods are used to simultaneously deposit a material on both surfaces and due to the surface treatment, the deposited material exhibits superior adherence qualities on both surfaces. In one embodiment, the structure is an opening formed in a semiconductor substrate and bounded by at least one portion of a crystalline silicon surface and at least one portion of an amorphous silicon oxide structure.Type: ApplicationFiled: November 19, 2015Publication date: June 30, 2016Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Lai-Wan CHONG, Wen-Chu HSIAO, Ying-Min CHOU, Hsiang-Hsiang KO -
Publication number: 20160181427Abstract: A semiconductor device includes an isolation feature in a substrate. The semiconductor device further includes a first source/drain feature in the substrate, wherein a first side of the first source/drain feature contacts the isolation feature, and the first source/drain feature exposes a portion of the isolation feature below a top surface of the substrate. The semiconductor device further includes a silicide layer over the first source/drain feature. The semiconductor device further includes a dielectric layer along the exposed portion of the isolation feature below the top surface of the substrate, wherein the dielectric layer contacts the silicide layer. The semiconductor device further includes a second source/drain feature in the substrate on an opposite side of a gate stack from the first source/drain feature, wherein the second source/drain feature has a substantially uniform thickness.Type: ApplicationFiled: March 2, 2016Publication date: June 23, 2016Inventors: Wen Chu HSIAO, Lai Wan CHONG, Chun-Chieh WANG, Ying Min CHOU, Hsiang Hsiang KO, Ying-Lang WANG
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Patent number: 9324863Abstract: A semiconductor device includes a source/drain feature in a substrate. The source/drain feature has an upper portion and a lower portion, the upper portion having a lower concentration of Ge than the lower portion. A Si-containing layer over the source/drain feature includes a metal silicide layer.Type: GrantFiled: May 2, 2014Date of Patent: April 26, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wen Chu Hsiao, Lai Wan Chong, Chun-Chieh Wang, Ying Min Chou, Hsiang Hsiang Ko, Ying-Lang Wang
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Surface tension modification using silane with hydrophobic functional group for thin film deposition
Patent number: 9214393Abstract: A semiconductor structure that includes crystalline surfaces and amorphous hydrophilic surfaces is provided. The hydrophilic surfaces are treated with silane that includes a hydrophobic functional group, converting the hydrophilic surfaces to hydrophobic surfaces. Chemical vapor deposition or other suitable deposition methods are used to simultaneously deposit a material on both surfaces and due to the surface treatment, the deposited material exhibits superior adherence qualities on both surfaces. In one embodiment, the structure is an opening formed in a semiconductor substrate and bounded by at least one portion of a crystalline silicon surface and at least one portion of an amorphous silicon oxide structure.Type: GrantFiled: April 2, 2012Date of Patent: December 15, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Lai Wan Chong, Wen Chu Hsiao, Ying Min Chou, Hsiang Hsiang Ko -
Publication number: 20150311314Abstract: A method includes providing a gate structure over a semiconductor substrate and forming a source/drain region associated with the gate structure by etching an opening in the semiconductor substrate, performing a first epitaxial growth process while an entirety of a sidewall of the opening is exposed to grow a first epitaxy material in the opening. The first epitaxial growth process is free of a first dopant impurity. A second epitaxial growth process is performed after first epitaxial growth process to grow a second epitaxy material on the first epitaxy material. The second epitaxy material has the first dopant impurity at a first concentration. Further, a third epitaxial growth process is performed after the second epitaxial growth process that includes introducing the first dopant impurity at a second concentration, the second concentration greater than the first concentration.Type: ApplicationFiled: June 19, 2015Publication date: October 29, 2015Inventors: Wen Chu Hsiao, Ju Wen Hsiao, Ying Min Chou, Hsiang Hsiang Ko, Ying-Lang Wang
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Publication number: 20150255578Abstract: A semiconductor device includes a gate structure located on a substrate and a raised source/drain region adjacent to the gate structure. The raised source/drain region includes: a first epitaxial-grown doped layer of the raised source/drain region in contact with the substrate; a second epitaxial-grown doped layer on the first epitaxial-grown doped layer and including a same dopant species as the first epitaxial-grown doped layer, wherein the second epitaxial-grown doped layer includes a higher dopant concentration than the first epitaxial-grown doped layer and interfacing the gate structure by using a predetermined distance; and a third epitaxial-grown doped layer on the second epitaxial-grown doped layer and including the same dopant species as the first epitaxial-grown doped layer, wherein the third epitaxial-grown doped layer includes a higher dopant concentration than the second epitaxial-grown doped layer.Type: ApplicationFiled: March 10, 2014Publication date: September 10, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: SHIH-CHIEH CHANG, YING-MIN CHOU, YI-MING HUANG, WEN-CHU HSIAO, HSIU-TING CHEN, HUAI-TEI YANG
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Publication number: 20150255602Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes proving a substrate. The substrate includes a gate stack over the substrate and source/drain regions separated by the gate stack. A first dislocation with a first pinch-point is formed within the source/drain region with a first depth. A second dislocation with a second pinch-point is formed within the source/drain region at a second depth. The second depth is substantial smaller than the first depth.Type: ApplicationFiled: March 7, 2014Publication date: September 10, 2015Applicant: Taiwan Semiconductor Manufacturing Company. Ltd.Inventors: Shiu-Ko JangJian, Chun-Chieh Wang, Shih-Chieh Chang, Ying-Min Chou
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Publication number: 20150236124Abstract: A semiconductor structure including a semiconductor substrate is provided. The semiconductor substrate includes a surface. A gate structure is provided on the surface. An interface lower than the surface is provided. An epitaxial regrowth region adjacent the gate structure is disposed on the interface. In addition, the epitaxial regrowth region extends over the surface and includes a bottom layer and a cap layer. The activation of the cap layer is lower than that of the bottom layer. Moreover, the bottom layer is lower than the surface and the gate structure. Furthermore, the bottom layer includes a first downwardly-curved edge and a second downwardly-curved edge over the first one. The first downwardly-curved edge is connected with the second downwardly-curved edge at two endpoints. The two endpoints are in contact with the surface of the semiconductor substrate.Type: ApplicationFiled: February 14, 2014Publication date: August 20, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: SHIH-CHIEH CHANG, YING-MIN CHOU, YI-MING HUANG, CHUN-JU HUANG, HUAI-TEI YANG, KEI-WEI CHEN
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Patent number: 9064892Abstract: A semiconductor structure and method for forming the same provide a high mobility stressor material suitable for use as source/drain regions or other active devices. The structure is formed in a substrate opening and is doped with an impurity such as boron in upper portions but is void of the impurity in regions that contact the surfaces of the opening. The structure is therefore resistant to out-diffusion of the dopant impurity during high temperature operations and may be formed through selective deposition using reduced pressure chemical vapor deposition or reduced pressure epitaxial deposition.Type: GrantFiled: August 30, 2011Date of Patent: June 23, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen Chu Hsiao, Ju Wen Hsiao, Ying Min Chou, Hsiang Hsiang Ko, Ying-Lang Wang
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Patent number: 8927406Abstract: A method for fabricating a dual damascene metal gate includes forming a dummy gate onto a substrate, disposing a protective layer on the substrate and the dummy gate, and growing an expanding layer on sides of the dummy gate. The method further includes removing the protective layer, forming a spacer around the dummy gate, and depositing and planarizing a dielectric layer. The method further includes selectively removing the expanding layer, and removing the dummy gate.Type: GrantFiled: January 10, 2013Date of Patent: January 6, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Chieh Wang, Wen-Chu Hsiao, Ying-Min Chou, Hsiang-Hsiang Ko
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Publication number: 20140239416Abstract: A semiconductor device includes a source/drain feature in a substrate. The source/drain feature has an upper portion and a lower portion, the upper portion having a lower concentration of Ge than the lower portion. A Si-containing layer over the source/drain feature includes a metal silicide layer.Type: ApplicationFiled: May 2, 2014Publication date: August 28, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wen Chu HSIAO, Lai Wan CHONG, Chun-Chieh WANG, Ying Min CHOU, Hsiang Hsiang KO, Ying-Lang WANG
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Patent number: 8735255Abstract: In a method of manufacturing a semiconductor device, a source/drain feature is formed over a substrate. A Si-containing layer is formed over the source/drain feature. A metal layer is formed over the Si-containing layer. A metal silicide layer is formed from the metal layer and Si in the Si-containing layer.Type: GrantFiled: May 1, 2012Date of Patent: May 27, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen Chu Hsiao, Lai Wan Chong, Chun-Chieh Wang, Ying Min Chou, Hsiang Hsiang Ko, Ying-Lang Wang