Patents by Inventor Ying-Ming Wang

Ying-Ming Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240404871
    Abstract: Methods for forming a dielectric isolation region between two active regions are disclosed herein. A mandrel is formed on a substrate, then etched to form a trench. Spacers are formed on the sidewalls of the mandrel. The mandrel is removed, and the substrate is etched to form fins extending in a first direction in the two active regions, and of fins extending in a second direction. A mask is formed that exposes the substrate between the fins extending in the second direction. The substrate is etched to form a trench. The trench is filled with a dielectric material up to the top of the fins to form the dielectric isolation region. The methods provide better depth control during etching between the two active regions, and also permit the trench to extend deeper into the substrate due to reduced depth/width ratios during the etching steps.
    Type: Application
    Filed: June 2, 2023
    Publication date: December 5, 2024
    Inventors: Wei Che Tsai, Yuan Tsung Tsai, Hsin-Yi Tsai, Ying Ming Wang, Hsien Hua Tseng, Shih-Hao Chen
  • Publication number: 20240322016
    Abstract: A semiconductor device and a method of forming the same are provided. A method includes forming a fin extending from a substrate. A sacrificial gate electrode layer is formed along a sidewall and a top surface of the fin. A patterning process is performed on the sacrificial gate electrode layer to form a sacrificial gate electrode. A reshaping process is performed on the sacrificial gate electrode to form a reshaped sacrificial gate electrode. The reshaped sacrificial gate electrode includes a first portion along the top surface of the fin and a second portion along the sidewall of the fin. A width of the first portion decreases as the first portion extends from a top surface of the first portion toward the top surface of the fin. A width of the second portion decreases as the second portion extends from the top surface of the fin toward the substrate.
    Type: Application
    Filed: May 30, 2024
    Publication date: September 26, 2024
    Inventors: Ru-Shang Hsiao, Ying Ming Wang, Ying Hsin Lu
  • Publication number: 20240231151
    Abstract: A display device includes a light source module, a housing, a display panel, a circuit board and a first flexible substrate. The housing includes a base plate, a sidewall and a support part. The base plate is below the light source module. The sidewall forms an accommodation space for the light source module. The support part is connected to the sidewall and extends away from the base plate, wherein the support part has a recess recessed towards the base plate. The display panel is above the light source module and the support part. The circuit board is below the support part, and the support part is located between the display panel and the circuit board. The first flexible substrate connects the light source module to the circuit board through the recess, wherein one side of the recess supports the display panel, and another side supports the circuit board.
    Type: Application
    Filed: October 31, 2023
    Publication date: July 11, 2024
    Applicant: AUO Corporation
    Inventors: Ying-Ming Wang, Ruei-Hung Tsai
  • Patent number: 12027609
    Abstract: A semiconductor device and a method of forming the same are provided. A method includes forming a fin extending from a substrate. A sacrificial gate electrode layer is formed along a sidewall and a top surface of the fin. A patterning process is performed on the sacrificial gate electrode layer to form a sacrificial gate electrode. A reshaping process is performed on the sacrificial gate electrode to form a reshaped sacrificial gate electrode. The reshaped sacrificial gate electrode includes a first portion along the top surface of the fin and a second portion along the sidewall of the fin. A width of the first portion decreases as the first portion extends from a top surface of the first portion toward the top surface of the fin. A width of the second portion decreases as the second portion extends from the top surface of the fin toward the substrate.
    Type: Grant
    Filed: July 28, 2022
    Date of Patent: July 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ru-Shang Hsiao, Ying Ming Wang, Ying Hsin Lu
  • Publication number: 20220367671
    Abstract: A semiconductor device and a method of forming the same are provided. A method includes forming a fin extending from a substrate. A sacrificial gate electrode layer is formed along a sidewall and a top surface of the fin. A patterning process is performed on the sacrificial gate electrode layer to form a sacrificial gate electrode. A reshaping process is performed on the sacrificial gate electrode to form a reshaped sacrificial gate electrode. The reshaped sacrificial gate electrode includes a first portion along the top surface of the fin and a second portion along the sidewall of the fin. A width of the first portion decreases as the first portion extends from a top surface of the first portion toward the top surface of the fin. A width of the second portion decreases as the second portion extends from the top surface of the fin toward the substrate.
    Type: Application
    Filed: July 28, 2022
    Publication date: November 17, 2022
    Inventors: Ru-Shang Hsiao, Ying Ming Wang, Ying Hsin Lu
  • Patent number: 11450758
    Abstract: A semiconductor device and a method of forming the same are provided. A method includes forming a fin extending from a substrate. A sacrificial gate electrode layer is formed along a sidewall and a top surface of the fin. A patterning process is performed on the sacrificial gate electrode layer to form a sacrificial gate electrode. A reshaping process is performed on the sacrificial gate electrode to form a reshaped sacrificial gate electrode. The reshaped sacrificial gate electrode includes a first portion along the top surface of the fin and a second portion along the sidewall of the fin. A width of the first portion decreases as the first portion extends from a top surface of the first portion toward the top surface of the fin. A width of the second portion decreases as the second portion extends from the top surface of the fin toward the substrate.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: September 20, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ru-Shang Hsiao, Ying Ming Wang, Ying Hsin Lu
  • Publication number: 20210391441
    Abstract: A semiconductor device and a method of forming the same are provided. A method includes forming a fin extending from a substrate. A sacrificial gate electrode layer is formed along a sidewall and a top surface of the fin. A patterning process is performed on the sacrificial gate electrode layer to form a sacrificial gate electrode. A reshaping process is performed on the sacrificial gate electrode to form a reshaped sacrificial gate electrode. The reshaped sacrificial gate electrode includes a first portion along the top surface of the fin and a second portion along the sidewall of the fin. A width of the first portion decreases as the first portion extends from a top surface of the first portion toward the top surface of the fin. A width of the second portion decreases as the second portion extends from the top surface of the fin toward the substrate.
    Type: Application
    Filed: June 12, 2020
    Publication date: December 16, 2021
    Inventors: Ru-Shang Hsiao, Ying Ming Wang, Ying Hsin Lu
  • Patent number: 10930783
    Abstract: Semiconductor devices, FinFET devices with optimized strained-source-drain recess profiles and methods of forming the same are provided. One of the semiconductor devices includes a substrate, a gate stack over the substrate and a strained layer in a recess of the substrate and aside the gate stack. Besides, a ratio of a depth at the greatest width of the recess to a width of the gate stack ranges from about 0.5 to 0.7.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: February 23, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ying Ting Hsia, Kun Yu Lin, Ying Ming Wang, Li-Te Hsu
  • Patent number: 10852469
    Abstract: A display panel includes an inner frame, a backlight module, an outer frame, and a light modulation module. The inner frame includes an inner surface forming a light guide plate accommodating area in a surrounding manner. The backlight module includes a light guide plate and a first optical film. The light guide plate is disposed in the light guide plate accommodating area, and the first optical film is carried on the inner frame. The outer frame includes a bottom portion and a sidewall portion that are connected to each other, in which the bottom portion and the sidewall portion form a receiving area, and the inner frame and the backlight module are located in the receiving area. The light modulation module is disposed on the first optical film. An orthogonal projection of the light modulation module in a vertical direction completely falls within the light guide plate accommodating area.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: December 1, 2020
    Assignee: AU OPTRONICS CORPORATION
    Inventor: Ying-Ming Wang
  • Publication number: 20190278017
    Abstract: A display panel includes an inner frame, a backlight module, an outer frame, and a light modulation module. The inner frame includes an inner surface forming a light guide plate accommodating area in a surrounding manner. The backlight module includes a light guide plate and a first optical film. The light guide plate is disposed in the light guide plate accommodating area, and the first optical film is carried on the inner frame. The outer frame includes a bottom portion and a sidewall portion that are connected to each other, in which the bottom portion and the sidewall portion form a receiving area, and the inner frame and the backlight module are located in the receiving area. The light modulation module is disposed on the first optical film. An orthogonal projection of the light modulation module in a vertical direction completely falls within the light guide plate accommodating area.
    Type: Application
    Filed: February 25, 2019
    Publication date: September 12, 2019
    Inventor: Ying-Ming Wang
  • Publication number: 20190081176
    Abstract: Semiconductor devices, FinFET devices with optimized strained-source-drain recess profiles and methods of forming the same are provided. One of the semiconductor devices includes a substrate, a gate stack over the substrate and a strained layer in a recess of the substrate and aside the gate stack. Besides, a ratio of a depth at the greatest width of the recess to a width of the gate stack ranges from about 0.5 to 0.7.
    Type: Application
    Filed: November 7, 2018
    Publication date: March 14, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ying Ting Hsia, Kun Yu Lin, Ying Ming Wang, Li-Te Hsu
  • Patent number: 10141443
    Abstract: Semiconductor devices, FinFET devices with optimized strained-source-drain recess profiles and methods of forming the same are provided. One of the semiconductor devices includes a substrate, a gate stack over the substrate and a strained layer in a recess of the substrate and aside the gate stack. Besides, a ratio of a depth at the greatest width of the recess to a width of the gate stack ranges from about 0.5 to 0.7.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: November 27, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ying Ting Hsia, Kun Yu Lin, Ying Ming Wang, Li-Te Hsu
  • Publication number: 20170278972
    Abstract: Semiconductor devices, FinFET devices with optimized strained-source-drain recess profiles and methods of forming the same are provided. One of the semiconductor devices includes a substrate, a gate stack over the substrate and a strained layer in a recess of the substrate and aside the gate stack. Besides, a ratio of a depth at the greatest width of the recess to a width of the gate stack ranges from about 0.5 to 0.7.
    Type: Application
    Filed: March 24, 2016
    Publication date: September 28, 2017
    Inventors: Ying Ting Hsia, Kun Yu Lin, Ying Ming Wang, Li-Te Hsu
  • Patent number: 7016410
    Abstract: A method for determining quantization numbers for each macro block in one video segment having a prescribed capacity is disclosed. The quantization numbers determine how much data will be preserved for that macro block. The method begins by determining a level of complexity for each macro block. Next, initial quantization numbers are chosen for the macro blocks by choosing the largest values possible without exceeding the prescribed capacity of the video segment. Final quantization numbers are selected based on respective ones of the initial quantization numbers proportioned according to the level of complexity for that macro block. The final quantization numbers may be increased or decreased so that the capacity of the video segment is maximized but not exceeded.
    Type: Grant
    Filed: August 23, 2002
    Date of Patent: March 21, 2006
    Assignee: ESS Technology, Inc.
    Inventors: Michael Chang, Ying-Ming Wang, Tai Jing
  • Publication number: 20040037356
    Abstract: A method for determining quantization numbers for each macro block in one video segment having a prescribed capacity is disclosed. The quantization numbers determine how much data will be preserved for that macro block. The method begins by determining a level of complexity for each macro block. Next, initial quantization numbers are chosen for the macro blocks by choosing the largest values possible without exceeding the prescribed capacity of the video segment. Final quantization numbers are selected based on respective ones of the initial quantization numbers proportioned according to the level of complexity for that macro block. The final quantization numbers may be increased or decreased so that the capacity of the video segment is maximized but not exceeded.
    Type: Application
    Filed: August 23, 2002
    Publication date: February 26, 2004
    Inventors: Michael Chang, Ying-Ming Wang, Tai Jing