Patents by Inventor Ying Ni

Ying Ni has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12026442
    Abstract: The disclosed relates to a hybrid traffic flow motion behavior modeling method based on an inference graph, wherein the method comprises: obtaining scene information, representing all traffic participants in the scene as vertices, and using directed edges to represent interaction relationships among traffic participants, so as to obtain the interaction graph; obtaining all possible interaction situations according to the interaction graph; based on each possible interaction situation, estimating the trajectory of each traffic participant in the interaction situation, and judging whether the trajectory conforms to a preset empirical decision-making criteria, so as to judge rationality of the interaction situation; and judging the rationality of all possible interaction situations obtained in the interaction situation generation step in turn until an interaction situation satisfying the rationality is found, and taking a trajectory of each traffic participant corresponding to the interaction situation as a fina
    Type: Grant
    Filed: May 31, 2023
    Date of Patent: July 2, 2024
    Assignee: TONGJI UNIVERSITY
    Inventors: Jian Sun, Donghao Zhou, Ying Ni
  • Publication number: 20230385487
    Abstract: The disclosed relates to a hybrid traffic flow motion behavior modeling method based on an inference graph, wherein the method comprises: obtaining scene information, representing all traffic participants in the scene as vertices, and using directed edges to represent interaction relationships among traffic participants, so as to obtain the interaction graph; obtaining all possible interaction situations according to the interaction graph; based on each possible interaction situation, estimating the trajectory of each traffic participant in the interaction situation, and judging whether the trajectory conforms to a preset empirical decision-making criteria, so as to judge rationality of the interaction situation; and judging the rationality of all possible interaction situations obtained in the interaction situation generation step in turn until an interaction situation satisfying the rationality is found, and taking a trajectory of each traffic participant corresponding to the interaction situation as a fina
    Type: Application
    Filed: May 31, 2023
    Publication date: November 30, 2023
    Applicant: TONGJI UNIVERSITY
    Inventors: Jian Sun, Donghao Zhou, Ying Ni
  • Patent number: 11040085
    Abstract: A pharmaceutical composition containing F1 polypeptide and/or F3 polypeptide and a use thereof are provided. The pharmaceutical composition is made into a common dosage form, such as an emulsion and an ointment, and used for treating a disease, such as a wart associated with a HPV infection, or a solid tumor associated with or not associated with the HPV infection.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: June 22, 2021
    Inventors: Tian-Fang Wang, Guo-Ying Ni, Xiao-Song Liu
  • Publication number: 20190374603
    Abstract: A pharmaceutical composition containing F1 polypeptide and/or F3 polypeptide and a use thereof are provided. The pharmaceutical composition is made into a common dosage form, such as an emulsion and an ointment, and used for treating a disease, such as a wart associated with a HPV infection, or a solid tumor associated with or not associated with the HPV infection.
    Type: Application
    Filed: June 27, 2019
    Publication date: December 12, 2019
    Inventors: Tian-Fang Wang, GUO-YING NI, XIAO-SONG LIU
  • Patent number: 8698325
    Abstract: An integrated circuit (IC) package includes an IC chip and a package carrier. The IC chip includes a substrate and an IC layered structure configured on an active surface of the substrate. The IC layered structure includes a first physical layer interface and a second physical layer interface. The first physical layer interface includes a plurality of first bump pads and a plurality of first inner pads electrically connected to the first bump pads, respectively. The second physical layer interface includes a plurality of second bump pads and a plurality of second inner pads electrically connected to the second bump pads, respectively. The second bump pads are mirror images of the first bump pads with respect to a first geometric plane perpendicular to the active surface. The second inner pads are mirror images of the first inner pads with respect to the first geometric plane.
    Type: Grant
    Filed: March 17, 2011
    Date of Patent: April 15, 2014
    Assignee: VIA Technologies, Inc.
    Inventors: Wen-Yuan Chang, Yu-Kai Chen, Yeh-Chi Hsu, Ying-Ni Lee, Wei-Chih Lai
  • Publication number: 20120098125
    Abstract: An integrated circuit (IC) package includes an IC chip and a package carrier. The IC chip includes a substrate and an IC layered structure configured on an active surface of the substrate. The IC layered structure includes a first physical layer interface and a second physical layer interface. The first physical layer interface includes a plurality of first bump pads and a plurality of first inner pads electrically connected to the first bump pads, respectively. The second physical layer interface includes a plurality of second bump pads and a plurality of second inner pads electrically connected to the second bump pads, respectively. The second bump pads are mirror images of the first bump pads with respect to a first geometric plane perpendicular to the active surface. The second inner pads are mirror images of the first inner pads with respect to the first geometric plane.
    Type: Application
    Filed: March 17, 2011
    Publication date: April 26, 2012
    Applicant: VIA TECHNOLOGIES, INC.
    Inventors: Wen-Yuan Chang, Yu-Kai Chen, Yeh-Chi Hsu, Ying-Ni Lee, Wei-Chih Lai
  • Patent number: 7615708
    Abstract: An arrangement of non-signal through vias suitable for a wiring board is provided. The wiring board has a contact surface, a core layer and pads. The contact pads are disposed on the contact surface, while the arrangement of non-signal through vias includes first non-signal through vias and a second non-signal through via. The first non-signal through vias pass through the core layer and are electrically connected to some of the contact pads. The second non-signal through via which passes through the core layer is disposed between the first non-signal through vias and is not electrically connected to the contact pads. The interval between the second non-signal through via and anyone of the surrounding first non-signal through vias is smaller than or equal to 0.72 times of the minimum interval between any two of the contact pads electrically connected to the corresponding first non-signal through vias.
    Type: Grant
    Filed: May 30, 2006
    Date of Patent: November 10, 2009
    Assignee: VIA Technologies, Inc.
    Inventors: Hsing-Chou Hsu, Ying-Ni Lee
  • Publication number: 20070194432
    Abstract: An arrangement of non-signal through vias suitable for a wiring board is provided. The wiring board has a contact surface, a core layer and pads. The contact pads are disposed on the contact surface, while the arrangement of non-signal through vias includes first non-signal through vias and a second non-signal through via. The first non-signal through vias pass through the core layer and are electrically connected to some of the contact pads. The second non-signal through via which passes through the core layer is disposed between the first non-signal through vias and is not electrically connected to the contact pads. The interval between the second non-signal through via and anyone of the surrounding first non-signal through vias is smaller than or equal to 0.72 times of the minimum interval between the second non-signal through via and one of the contact pads electrically connected to the corresponding first non-signal through vias.
    Type: Application
    Filed: May 30, 2006
    Publication date: August 23, 2007
    Inventors: Hsing-Chou Hsu, Ying-Ni Lee
  • Publication number: 20070096121
    Abstract: A light emitting diode and a method for manufacturing the same are provided. The light emitting diode includes: a transparent substrate made of AlxGa1-xAs; a light emitting layer made of AlGaInP, stacked on the transparent substrate, and having a multiple layered epitaxially growing structure; a window layer made of GaP, stacked on the light emitting layer, and having a transparent structure with a great bandgap; an upper electrode layer overlying the window layer; and a lower electrode layer underlying the transparent substrate, wherein the x-value in AlxGa1-xAs is set to corresponding to the emission wavelengths of the light emitting layer so that the transparent substrate can have a great bandgap which make it to be transparent to the light emitted by the light emitting layer; and a window layer is used to increase the current diffusion from the upper electrode layer to the light emitting layer.
    Type: Application
    Filed: October 28, 2005
    Publication date: May 3, 2007
    Inventors: Ying Ni, Kuo Nee, Ming Hung