Patents by Inventor YING PANG
YING PANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240097579Abstract: Disclosed are a parallel multi-converter and a capacity design method therefor. A first output current model and a second output current model are generated by respectively acquiring electrical parameters of an inductive voltage source converter and a capacitive voltage source converter, and the first output current model and the second output current model are integrated under the same output current condition, so that it may be ensured that the inductive voltage source converter and the capacitive voltage source converter have the same current generating ability; meanwhile, a coupling inductance relationship between the inductive voltage source converter and the capacitive voltage source converter is combined to further obtain the optimal capacity value of the inductive voltage source converter and the optimal capacity value of the capacitive voltage source converter. Therefore, the L-VSC and the LC-VSC have the same current generating ability, and the multi-converter has lower total voltage capacity.Type: ApplicationFiled: September 2, 2022Publication date: March 21, 2024Applicant: University of MacauInventors: Man-Chung WONG, Ying PANG
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Patent number: 11476164Abstract: Integrated circuit structures having differentiated workfunction layers are described. In an example, an integrated circuit structure includes a first gate electrode above a substrate. The first gate electrode includes a first workfunction material layer. A second gate electrode is above the substrate. The second gate electrode includes a second workfunction material layer different in composition from the first workfunction material layer. The second gate electrode does not include the first workfunction material layer, and the first gate electrode does not include the second workfunction material layer. A third gate electrode above is the substrate. The third gate electrode includes a third workfunction material layer different in composition from the first workfunction material layer and the second workfunction material layer. The third gate electrode does not include the first workfunction material layer and does not include the second workfunction material layer.Type: GrantFiled: September 26, 2017Date of Patent: October 18, 2022Assignee: Intel CorporationInventors: Ying Pang, Florian Gstrein, Dan S. Lavric, Ashish Agrawal, Robert Niffenegger, Padmanava Sadhukhan, Robert W. Heussner, Joel M. Gregie
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Patent number: 10755984Abstract: Techniques are disclosed for customization of fin-based transistor devices to provide a diverse range of channel configurations and/or material systems, and within the same integrated circuit die. Sacrificial fins are removed via wet and/or dry etch chemistries configured to provide trench bottoms that are non-faceted and have no or otherwise low-ion damage. The trench is then filled with desired semiconductor material. A trench bottom having low-ion damage and non-faceted morphology encourages a defect-free or low defect interface between the substrate and the replacement material. In an embodiment, each of a first set of the sacrificial silicon fins is recessed and replaced with a p-type material, and each of a second set of the sacrificial fins is recessed and replaced with an n-type material. Another embodiment may include a combination of native fins (e.g., Si) and replacement fins (e.g., SiGe). Another embodiment may include replacement fins all of the same configuration.Type: GrantFiled: June 24, 2015Date of Patent: August 25, 2020Assignee: Intel CorporationInventors: Glenn A. Glass, Ying Pang, Nabil G. Mistkawi, Anand S. Murthy, Tahir Ghani, Huang-Lin Chao
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Publication number: 20200219775Abstract: Integrated circuit structures having differentiated workfunction layers are described. In an example, an integrated circuit structure includes a first gate electrode above a substrate. The first gate electrode includes a first workfunction material layer. A second gate electrode is above the substrate. The second gate electrode includes a second workfunction material layer different in composition from the first workfunction material layer. The second gate electrode does not include the first workfunction material layer, and the first gate electrode does not include the second workfunction material layer. A third gate electrode above is the substrate. The third gate electrode includes a third workfunction material layer different in composition from the first workfunction material layer and the second workfunction material layer. The third gate electrode does not include the first workfunction material layer and does not include the second workfunction material layer.Type: ApplicationFiled: September 26, 2017Publication date: July 9, 2020Inventors: Ying PANG, Florian GSTREIN, Dan S. LAVRIC, Ashish AGRAWAL, Robert NIFFENEGGER, Padmanava SADHUKHAN, Robert W. HEUSSNER, Joel M. GREGIE
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Patent number: 10541334Abstract: Techniques are disclosed for improved integration of germanium (Ge)-rich p-MOS source/drain contacts to, for example, reduce contact resistance. The techniques include depositing the p-type Ge-rich layer directly on a silicon (Si) surface in the contact trench location, because Si surfaces are favorable for deposition of high quality conductive Ge-rich materials. In one example method, the Ge-rich layer is deposited on a surface of the Si substrate in the source/drain contact trench locations, after removing a sacrificial silicon germanium (SiGe) layer previously deposited in the source/drain locations. In another example method, the Ge-rich layer is deposited on a Si cladding layer in the contact trench locations, where the Si cladding layer is deposited on a functional p-type SiGe layer. In some cases, the Ge-rich layer comprises at least 50% Ge (and may contain tin (Sn) and/or Si) and is boron (B) doped at levels above 1E20 cm?3.Type: GrantFiled: November 26, 2018Date of Patent: January 21, 2020Assignee: INTEL CORPORATIONInventors: Glenn A. Glass, Anand S. Murthy, Tahir Ghani, Ying Pang, Nabil G. Mistkawi
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Patent number: 10510848Abstract: Techniques are disclosed for reducing off-state leakage of fin-based transistors through the use of a sub-fin passivation layer. In some cases, the techniques include forming sacrificial fins in a bulk silicon substrate and depositing and planarizing shallow trench isolation (STI) material, removing and replacing the sacrificial silicon fins with a replacement material (e.g., SiGe or III-V material), removing at least a portion of the STI material to expose the sub-fin areas of the replacement fins, applying a passivating layer/treatment/agent to the exposed sub-fins, and re-depositing and planarizing additional STI material. Standard transistor forming processes can then be carried out to complete the transistor device. The techniques generally provide the ability to add arbitrary passivation layers for structures that are grown in STI-based trenches. The passivation layer inhibits sub-fin source-to-drain (and drain-to-source) current leakage.Type: GrantFiled: June 24, 2015Date of Patent: December 17, 2019Assignee: Intel CorporationInventors: Glenn A. Glass, Ying Pang, Anand S. Murthy, Tahir Ghani, Karthik Jambunathan
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Publication number: 20190305102Abstract: A PMOS gate structure is described. The PMOS gate structure includes a trench, a high-k metal layer on a bottom and on sidewalls of the trench and a flourine free tungsten layer on the surface of the high-k metal. The PMOS gate structure also includes a metal layer in a space in the n-type work function metal.Type: ApplicationFiled: April 2, 2018Publication date: October 3, 2019Inventors: Dan S. LAVRIC, Ying PANG
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Patent number: 10274458Abstract: A method for detecting a surface coating performance of a cathode active material comprising: providing an acid solution with a predetermined concentration; putting a coated cathode active material in a container; adding the acid solution into the container until the coated cathode active material is completely soaked to form a solid liquid mixture; sealing the container, heating and stirring the solid liquid mixture, and recording a series of pH values of a liquid phase of the solid liquid mixture at different points in time; and determining the surface coating performance of the coated cathode active material by comparing the recorded pH values with standard pH values. A method for detecting a surface coating performance of a cathode active material by detecting metal ion concentrations in the solid liquid mixture is also provided.Type: GrantFiled: April 17, 2018Date of Patent: April 30, 2019Assignee: TSINGHUA UNIVERSITYInventors: Li Wang, Xiang-Ming He, Xiao-Ying Pang
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Publication number: 20190109234Abstract: Techniques are disclosed for improved integration of germanium (Ge)-rich p-MOS source/drain contacts to, for example, reduce contact resistance. The techniques include depositing the p-type Ge-rich layer directly on a silicon (Si) surface in the contact trench location, because Si surfaces are favorable for deposition of high quality conductive Ge-rich materials. In one example method, the Ge-rich layer is deposited on a surface of the Si substrate in the source/drain contact trench locations, after removing a sacrificial silicon germanium (SiGe) layer previously deposited in the source/drain locations. In another example method, the Ge-rich layer is deposited on a Si cladding layer in the contact trench locations, where the Si cladding layer is deposited on a functional p-type SiGe layer. In some cases, the Ge-rich layer comprises at least 50% Ge (and may contain tin (Sn) and/or Si) and is boron (B) doped at levels above 1E20 cm?3.Type: ApplicationFiled: November 26, 2018Publication date: April 11, 2019Applicant: INTEL CORPORATIONInventors: GLENN A. GLASS, ANAND S. MURTHY, TAHIR GHANI, YING PANG, NABIL G. MISTKAWI
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Patent number: 10147817Abstract: Techniques are disclosed for improved integration of germanium (Ge)-rich p-MOS source/drain contacts to, for example, reduce contact resistance. The techniques include depositing the p-type Ge-rich layer directly on a silicon (Si) surface in the contact trench location, because Si surfaces are favorable for deposition of high quality conductive Ge-rich materials. In one example method, the Ge-rich layer is deposited on a surface of the Si substrate in the source/drain contact trench locations, after removing a sacrificial silicon germanium (SiGe) layer previously deposited in the source/drain locations. In another example method, the Ge-rich layer is deposited on a Si cladding layer in the contact trench locations, where the Si cladding layer is deposited on a functional p-type SiGe layer. In some cases, the Ge-rich layer comprises at least 50% Ge (and may contain tin (Sn) and/or Si) and is boron (B) doped at levels above 1E20 cm?3.Type: GrantFiled: January 2, 2018Date of Patent: December 4, 2018Assignee: INTEL CORPORATIONInventors: Glenn A. Glass, Anand S. Murthy, Tahir Ghani, Ying Pang, Nabil G. Mistkawi
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Publication number: 20180238828Abstract: A method for detecting a surface coating performance of a cathode active material comprising: providing an acid solution with a predetermined concentration; putting a coated cathode active material in a container; adding the acid solution into the container until the coated cathode active material is completely soaked to form a solid liquid mixture; sealing the container, heating and stirring the solid liquid mixture, and recording a series of pH values of a liquid phase of the solid liquid mixture at different points in time; and determining the surface coating performance of the coated cathode active material by comparing the recorded pH values with standard pH values. A method for detecting a surface coating performance of a cathode active material by detecting metal ion concentrations in the solid liquid mixture is also provided.Type: ApplicationFiled: April 17, 2018Publication date: August 23, 2018Applicant: Tsinghua UniversityInventors: LI WANG, XIANG-MING HE, XIAO-YING PANG
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Publication number: 20180197789Abstract: Techniques are disclosed for customization of fin-based transistor devices to provide a diverse range of channel configurations and/or material systems, and within the same integrated circuit die. Sacrificial fins are removed via wet and/or dry etch chemistries configured to provide trench bottoms that are non-faceted and have no or otherwise low-ion damage. The trench is then filled with desired semiconductor material. A trench bottom having low-ion damage and non-faceted morphology encourages a defect-free or low defect interface between the substrate and the replacement material. In an embodiment, each of a first set of the sacrificial silicon fins is recessed and replaced with a p-type material, and each of a second set of the sacrificial fins is recessed and replaced with an n-type material. Another embodiment may include a combination of native fins (e.g., Si) and replacement fins (e.g., SiGe). Another embodiment may include replacement fins all of the same configuration.Type: ApplicationFiled: June 24, 2015Publication date: July 12, 2018Applicant: INTEL CORPORATIONInventors: GLENN A. GLASS, YING PANG, NABIL G. MISTKAWI, ANAND S. MURTHY, TAHIR GHANI, HUANG-LIN CHAO
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Publication number: 20180151677Abstract: Techniques are disclosed for reducing off-state leakage of fin-based transistors through the use of a sub-fin passivation layer. In some cases, the techniques include forming sacrificial fins in a bulk silicon substrate and depositing and planarizing shallow trench isolation (STI) material, removing and replacing the sacrificial silicon fins with a replacement material (e.g., SiGe or III-V material), removing at least a portion of the STI material to expose the sub-fin areas of the replacement fins, applying a passivating layer/treatment/agent to the exposed sub-fins, and re-depositing and planarizing additional STI material. Standard transistor forming processes can then be carried out to complete the transistor device. The techniques generally provide the ability to add arbitrary passivation layers for structures that are grown in STI-based trenches. The passivation layer inhibits sub-fin source-to-drain (and drain-to-source) current leakage.Type: ApplicationFiled: June 24, 2015Publication date: May 31, 2018Applicant: INTEL CORPORATIONInventors: GLENN A. GLASS, YING PANG, ANAND S. MURTHY, TAHIR GHANI, KARTHIK JAMBUNATHAN
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Publication number: 20180145174Abstract: Techniques are disclosed for improved integration of germanium (Ge)-rich p-MOS source/drain contacts to, for example, reduce contact resistance. The techniques include depositing the p-type Ge-rich layer directly on a silicon (Si) surface in the contact trench location, because Si surfaces are favorable for deposition of high quality conductive Ge-rich materials. In one example method, the Ge-rich layer is deposited on a surface of the Si substrate in the source/drain contact trench locations, after removing a sacrificial silicon germanium (SiGe) layer previously deposited in the source/drain locations. In another example method, the Ge-rich layer is deposited on a Si cladding layer in the contact trench locations, where the Si cladding layer is deposited on a functional p-type SiGe layer. In some cases, the Ge-rich layer comprises at least 50% Ge (and may contain tin (Sn) and/or Si) and is boron (B) doped at levels above 1E20 cm?3.Type: ApplicationFiled: January 2, 2018Publication date: May 24, 2018Applicant: INTEL CORPORATIONInventors: GLENN A. GLASS, ANAND S. MURTHY, TAHIR GHANI, YING PANG, NABIL G. MISTKAWI
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Patent number: 9859424Abstract: Techniques are disclosed for improved integration of germanium (Ge)-rich p-MOS source/drain contacts to, for example, reduce contact resistance. The techniques include depositing the p-type Ge-rich layer directly on a silicon (Si) surface in the contact trench location, because Si surfaces are favorable for deposition of high quality conductive Ge-rich materials. In one example method, the Ge-rich layer is deposited on a surface of the Si substrate in the source/drain contact trench locations, after removing a sacrificial silicon germanium (SiGe) layer previously deposited in the source/drain locations. In another example method, the Ge-rich layer is deposited on a Si cladding layer in the contact trench locations, where the Si cladding layer is deposited on a functional p-type SiGe layer. In some cases, the Ge-rich layer comprises at least 50% Ge (and may contain tin (Sn) and/or Si) and is boron (B) doped at levels above 1E20 cm?3.Type: GrantFiled: March 21, 2014Date of Patent: January 2, 2018Assignee: INTEL CORPORATIONInventors: Glenn A. Glass, Anand S. Murthy, Tahir Ghani, Ying Pang, Nabil G. Mistkawi
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Publication number: 20170012124Abstract: Techniques are disclosed for improved integration of germanium (Ge)-rich p-MOS source/drain contacts to, for example, reduce contact resistance. The techniques include depositing the p-type Ge-rich layer directly on a silicon (Si) surface in the contact trench location, because Si surfaces are favorable for deposition of high quality conductive Ge-rich materials. In one example method, the Ge-rich layer is deposited on a surface of the Si substrate in the source/drain contact trench locations, after removing a sacrificial silicon germanium (SiGe) layer previously deposited in the source/drain locations. In another example method, the Ge-rich layer is deposited on a Si cladding layer in the contact trench locations, where the Si cladding layer is deposited on a functional p-type SiGe layer. In some cases, the Ge-rich layer comprises at least 50% Ge (and may contain tin (Sn) and/or Si) and is boron (B) doped at levels above 1E20 cm?3.Type: ApplicationFiled: March 21, 2014Publication date: January 12, 2017Applicant: INTEL CORPORATIONInventors: GLENN A. GLASS, ANAND S. MURTHY, TAHIR GHANI, YING PANG, NABIL G. MISTKAWI