Patents by Inventor Ying PEI

Ying PEI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12453157
    Abstract: The MOS device with resistive field plate for realizing conductance modulation field effect in the present invention is based on the existing trench gate MOS device, and a semi-insulating resistive field plate electrically connected to the trench gate structure and the drain structure is added in the drift region, where the trench gate structure can control the on-off of the MOS channel, and the semi-insulating resistive field plate can adjust the doping concentration of the drift region to modulate the conductance of the on-state drift region and the distribution of off-state high-voltage blocking electric field, thus a lower on-resistance can be obtained. In addition, the modern 2.5-dimensional processing technology based on deep trench etching is adopted in the present invention, which is conducive to the miniaturization design and high density design of the structure and is more suitable for the More than Moore (beyond Moore) development of modern integrated semiconductor devices.
    Type: Grant
    Filed: April 26, 2021
    Date of Patent: October 21, 2025
    Assignee: NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION
    Inventors: Kaizhou Tan, Tian Xiao, Jiahao Zhang, Yonghui Yang, Xiaoquan Li, Pengfei Wang, Ying Pei, Guangbo Li, Hequan Jiang, Peijian Zhang, Sheng Qiu, Liang Chen, Wei Cui
  • Publication number: 20250169141
    Abstract: The present application provides a high-voltage power semiconductor device and a method for manufacturing the same. A plurality of second resistive field plate structures is arranged in a terminal region of an epitaxial layer and extends through the epitaxial layer in a first direction to a substrate. The second resistive field plate structures are arranged concentrically and discontinuously around an active region in a first plane. The second resistive field plate structures and a third resistive field plate structure thereon form a ?-type combined resistive field plate structure.
    Type: Application
    Filed: January 17, 2025
    Publication date: May 22, 2025
    Applicant: NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION
    Inventors: Kaizhou TAN, Tian XIAO, Xiaoquan LI, Xueliang XU, Ying WANG, Yongqing JIANG, Yuxin WANG, Guangbo LI, Pengfei WANG, Ying PEI, Jian WU, Ruzhang LI, Zhikuan WANG, Sheng QIU, Peijian ZHANG, Zhengyuan ZHANG, Yukui LIU
  • Publication number: 20250113820
    Abstract: Provided herein systems and methods for processing cryopreserved cells without an expansion phase after thawing, including transfecting cells for gene editing purposes and cryopreserving transfected cells. Systems and methods for high-throughput processing of frozen cells are also provided. The systems and methods provided can be used to modify cells, including gene editing, in cell arrays.
    Type: Application
    Filed: July 18, 2024
    Publication date: April 10, 2025
    Inventors: Bryant FLORES, Ying PEI, Alexander BROWN
  • Publication number: 20240268371
    Abstract: Provided herein systems and methods for processing cryopreserved cells without an expansion phase after thawing, including transfecting cells for gene editing purposes and cryopreserving transfected cells. Systems and methods for high-throughput processing of frozen cells are also provided. The systems and methods provided can be used to modify cells, including gene editing, in cell arrays.
    Type: Application
    Filed: February 14, 2024
    Publication date: August 15, 2024
    Inventors: Bryant FLORES, Ying PEI, Alexander BROWN
  • Publication number: 20240038853
    Abstract: The MOS device with resistive field plate for realizing conductance modulation field effect in the present invention is based on the existing trench gate MOS device, and a semi-insulating resistive field plate electrically connected to the trench gate structure and the drain structure is added in the drift region, where the trench gate structure can control the on-off of the MOS channel, and the semi-insulating resistive field plate can adjust the doping concentration of the drift region to modulate the conductance of the on-state drift region and the distribution of off-state high-voltage blocking electric field, thus a lower on-resistance can be obtained. In addition, the modern 2.5-dimensional processing technology based on deep trench etching is adopted in the present invention, which is conducive to the miniaturization design and high density design of the structure and is more suitable for the More than Moore (beyond Moore) development of modern integrated semiconductor devices.
    Type: Application
    Filed: April 26, 2021
    Publication date: February 1, 2024
    Applicant: NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION
    Inventors: Kaizhou TAN, Tian XIAO, Jiahao ZHANG, Yonghui YANG, Xiaoquan LI, Pengfei WANG, Ying PEI, Guangbo LI, Hequan JIANG, Peijian ZHANG, Sheng QIU, Liang CHEN, Wei CUI
  • Publication number: 20230411464
    Abstract: A shared-dielectric MOSFET device with a resistive-field-plate and a preparation method are provided. In the shared-dielectric MOSFET device, the semi-insulating resistive-field-plate electrically connected to the trench gate structure and the drain structure is introduced in the drift region of the existing trench gate MOS devices, and when the trench gate structure controls the MOS channel to be turned on or turned off, the semi-insulating resistive-field-plate can adjust the doping concentration of the drift region, to modulate the conductance of the on-state drift region and the distribution of a off-state high-voltage blocking electric field, thereby obtaining a lower on-resistance. Meanwhile, in the preparation method of the present disclosure, the modern 2.
    Type: Application
    Filed: November 1, 2021
    Publication date: December 21, 2023
    Applicant: NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION
    Inventors: Kaizhou TAN, Tian XIAO, Jiahao ZHANG, Xiaoquan LI, Pengfei WANG, Ying PEI, Guangbo LI, Yonghui YANG, Hequan JIANG, Peijian ZHANG, Sheng QIU, Liang CHEN, Wei CUI