Abstract: Circuits, systems, and methods for protecting an integrated circuit having independently-powered circuit sections from electrostatic discharge events. The integrated circuit generally comprises an ESD control line, a first circuit having a first electrostatic discharge (ESD) device coupled to a first positive voltage rail, a first negative voltage rail, and the ESD control line, the first ESD device configured to activate an ESD control signal on the ESD control line when an electrostatic discharge occurs, and a second circuit having a second positive voltage rail, a second negative voltage rail, and a second ESD device, coupled to the second positive voltage rail, the second negative voltage rail, and the ESD control line, the second ESD device configured to shunt current between the second positive voltage rail and the second negative voltage rail when the ESD control signal is activated.

Abstract: Circuits, systems, and methods for protecting an integrated circuit device having a first power rail and a second power rail from electrostatic discharge (ESD) events. The ESD protection circuit generally comprises an ESD shunt device coupled to the first power rail and a ground potential, a bias circuit configured to provide a bias voltage to the ESD shunt device during a normal mode of operation and to disable the bias voltage during an ESD event on the first power rail, and an isolation circuit configured to isolate the second power rail from the ESD shunt device during the normal mode of operation and to couple the second power rail to the ESD shunt device during an ESD event on the second power rail. The present invention advantageously provides ESD protection that can be shared by independent power supply rails with minimal current leakage through the ESD device, thereby reducing the total number of ESD protection circuits on a mixed supply integrated circuit device.

Abstract: A system includes a complementary metal oxide semiconductor (CMOS) receiver, a first transistor, and a tracking circuit. The tracking circuit receives an input voltage and a reference voltage and selectively biases the first transistor to one of the input voltage and the reference voltage based on a comparison of the input voltage and the reference voltage. The CMOS receiver generates an output signal based on said comparison.