Abstract: A system may include a first integrated circuit die comprising a first upper surface, an integrated circuit package substrate comprising a second upper surface, a wire coupled to the a first upper surface and to the second upper surface, a plurality of elements coupled to the first upper surface, and a second integrated circuit die coupled to the plurality of elements. A portion of the wire is disposed between the first integrated circuit die and the second integrated circuit die.

Abstract: A method for fabricating semiconductor packages is proposed. A plurality of substrates each having a chip thereon are prepared. Each substrate has similar length and width to the predetermined length and width of the semiconductor package. A carrier having a plurality of openings is prepared. Each opening is larger in length and width than the substrate. The substrates are positioned in the corresponding openings, and gaps between the substrates and the carrier are sealed. A molding process is performed to form an encapsulant over each opening to encapsulate the chip. An area on the carrier covered by the encapsulant is larger in length and width than the opening. After performing a mold-releasing process, a plurality of the semiconductor packages are formed by a singulation process to cut along substantially edges of each substrate according to the predetermined size of the semiconductor package. A waste of substrate material is avoided.

Abstract: A bump structure of a semiconductor package and a method for fabricating the same are provided. The bump structure is used to connect a semiconductor element to a carrier of the semiconductor package. The fabrication method primarily employs an electroplating process to form the bump structure including an under bump metallurgy (UBM) layer, at least one I-shaped conductive pillar, and a solder material. This allows fine-pitch electrical connection pads to be arranged in the semiconductor package, and also provides an enhanced support structure and a sufficient height between the semiconductor element and the carrier.

Abstract: A method for fabricating semiconductor packages includes the steps of: providing a plurality of substrates and a carrier having a plurality of openings, wherein, each of the substrates has at least one chip (die) disposed thereon, length and width of the substrates are approximately equal to the predefined length and width of semiconductor packages, and length and width of the openings of the carrier are bigger than length and width of the substrates; respectively positioning the substrates in the openings of the carrier and blocking the gaps between the substrates and the carrier so as to prevent the gaps from penetrating through the carrier; performing a mold press process so as to form an encapsulant on each of the openings for encapsulating the chip, wherein length and width of the area covered by the encapsulant are bigger than length and width of the opening; performing a mold releasing process; and cutting along edges of the substrates according to the predefined length and width of semiconductor packa

Abstract: A method for positioning a semiconductor component is disclosed. The method includes providing the semiconductor component and a carrier, the carrier having a plurality of openings, a protruded portion being provided at each corner position of each of the openings and extended toward a center of the opening, a distance between two diagonal protruded portions of the opening being slightly larger than that between two diagonal corners of the semiconductor component; and positioning the semiconductor component in the openings of the carrier via the protruded portions provided at each corner position of each of the openings.

Abstract: A semiconductor device with reinforced under-support structure and a method for fabricating the semiconductor device are provided, which can be used in the packaging of an MPBGA/TFBGA (Multi-Package Ball Grid Array & Thin Fine-pitch Ball Grid Array) module to help reinforce the TFBGA under-support structure therein. The proposed chip-packaging method is characterized by the provision of large-area solder pads at the corners of a solder-pad array used for TFBGA attaching application, in order to form solder bumps of a large cross section and volume during reflow process to help reinforce the TFBGA under-package structure. This feature can reinforce the TFBGA under-package structure without having to use flip-chip underfill technology, and without having to use extra large type solder balls and arrange pads into different pitches as in the prior art.

Abstract: A ground pad structure for preventing solder extrusion and a semiconductor package having the ground pad structure are disclosed, wherein the ground pad structure has the ground pads located along the circumference of its ground plane be formed in a non-solder mask defined manner. Accordingly, a good grounding quality is maintained, and the occurrence of the electrical bridging among the adjacent conductive traces can be avoided as the extrusion of the molten solder bumps from the ground pads located along the ground pad structure's circumference toward their adjacent conductive traces is effectively prevented.

Abstract: A method for fabricating semiconductor packages is proposed. A plurality of substrates are prepared each having a chip thereon. Length and width of each substrate are equal to predetermined length and width of the semiconductor package. A carrier having a plurality of openings is prepared. A protruded portion is formed at each corner of each opening, wherein a distance between two diagonal protruded portions is slightly larger than that between two diagonal corners of the substrate. The substrates are fixed in the openings of the carrier by means of the protruded portions, and gaps between the substrates and the carrier are sealed. An encapsulant is formed over each opening to encapsulate the corresponding chip by a molding process. An area on the carrier covered by the encapsulant is larger in length and width than the opening. A plurality of the semiconductor packages are formed after performing mold-releasing and singulation processes.

Abstract: A bump structure of a semiconductor package and a method for fabricating the same are provided. The bump structure is used to connect a semiconductor element to a carrier of the semiconductor package. The fabrication method primarily employs an electroplating process to form the bump structure including an under bump metallurgy (UBM) layer, at least one I-shaped conductive pillar, and a solder material. This allows fine-pitch electrical connection pads to be arranged in the semiconductor package, and also provides an enhanced support structure and a sufficient height between the semiconductor element and the carrier.

Abstract: A method for fabricating semiconductor packages is proposed. A plurality of substrates each having a chip thereon are prepared. Each substrate has similar length and width to the predetermined length and width of the semiconductor package. A carrier having a plurality of openings is prepared. Each opening is larger in length and width than the substrate. The substrates are positioned in the corresponding openings, and gaps between the substrates and the carrier are sealed. A molding process is performed to form an encapsulant over each opening to encapsulate the chip. An area on the carrier covered by the encapsulant is larger in length and width than the opening. After performing a mold-releasing process, a plurality of the semiconductor packages are formed by a singulation process to cut along substantially edges of each substrate according to the predetermined size of the semiconductor package. A waste of substrate material is avoided.

Abstract: A method for fabricating semiconductor packages is proposed. A plurality of substrates are prepared each having a chip thereon. Length and width of each substrate are equal to predetermined length and width of the semiconductor package. A carrier having a plurality of openings is prepared. A protruded portion is formed at each corner of each opening, wherein a distance between two diagonal protruded portions is slightly larger than that between two diagonal corners of the substrate. The substrates are fixed in the openings of the carrier by means of the protruded portions, and gaps between the substrates and the carrier are sealed. An encapsulant is formed over each opening to encapsulate the corresponding chip by a molding process. An area on the carrier covered by the encapsulant is larger in length and width than the opening. A plurality of the semiconductor packages are formed after performing mold-releasing and singulation processes.

Abstract: A thermally enhanced semiconductor package with EMI (electric and magnetic interference) shielding is provided in which a chip is mounted on and electrically connected to a surface of a substrate, and a thermally conductive member is stacked on the chip and electrically coupled to the surface of the substrate by bonding wires. An encapsulant is formed and encapsulates the chip, thermally conductive member, and bonding wires. A plurality of solder balls are implanted on an opposite surface of the substrate. The thermally conductive member is grounded via the bonding wires, substrate, and solder balls, and provides an EMI shielding effect for the chip to protect the chip against external electric and magnetic interference. The thermally conductive member has a coefficient of thermal expansion similar to that of the chip, and reduces thermal stress exerted on the chip and enhances mechanical strength of the chip to thereby prevent chip cracks.

Abstract: A ground pad structure for preventing solder extrusion and a semiconductor package having the ground pad structure are disclosed, wherein the ground pad structure has the ground pads located along the circumference of its ground plane be formed in a non-solder mask defined manner. Accordingly, a good grounding quality is maintained, and the occurrence of the electrical bridging among the adjacent conductive traces can be avoided as the extrusion of the molten solder bumps from the ground pads located along the ground pad structure's circumference toward their adjacent conductive traces is effectively prevented.

Abstract: A thermally enhanced semiconductor package with EMI (electric and magnetic interference) shielding is provided in which a chip is mounted on and electrically connected to a surface of a substrate, and a thermally conductive member is stacked on the chip and electrically coupled to the surface of the substrate by bonding wires. An encapsulant is formed and encapsulates the chip, thermally conductive member, and bonding wires. A plurality of solder balls are implanted on an opposite surface of the substrate. The thermally conductive member is grounded via the bonding wires, substrate, and solder balls, and provides an EMI shielding effect for the chip to protect the chip against external electric and magnetic interference. The thermally conductive member has a coefficient of thermal expansion similar to that of the chip, and reduces thermal stress exerted on the chip and enhances mechanical strength of the chip to thereby prevent chip cracks.

Abstract: A semiconductor device with reinforced under-support structure and a method for fabricating the semiconductor device are provided, which can be used in the packaging of an MPBGA/TFBGA (Multi-Package Ball Grid Array & Thin Fine-pitch Ball Grid Array) module to help reinforce the TFBGA under-support structure therein. The proposed chip-packaging method is characterized by the provision of large-area solder pads at the corners of a solder-pad array used for TFBGA attaching application, in order to form solder bumps of a large cross section and volume during reflow process to help reinforce the TFBGA under-package structure. This feature can reinforce the TFBGA under-package structure without having to use flip-chip underfill technology, and without having to use extra large type solder balls and arrange pads into different pitches as in the prior art.