Patents by Inventor Ying Ren
Ying Ren has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8765443Abstract: Disclosed herein are a crystal of a human TOPII (hTOPII)-DNA binary complex, the method for preparing the same and the use thereof. The hTOPII-DNA binary complex includes an hTOPII portion that contains an hTOPII core domain (hTOPIIcore), and a synthetic double-stranded DNA in complex with the hTOPII portion. The synthetic double-stranded DNA has a first DNA strand comprising nucleotide positions 3 to 20 of the sequence of 5?-NNNCCGAGCNNNNGCTCGGNNN-3? (SEQ ID NO: 1), wherein N is any one of adenine, thymine, cytosine, or guanine, and a second DNA strand complementary to the first DNA strand.Type: GrantFiled: July 24, 2012Date of Patent: July 1, 2014Assignee: National Taiwan UniversityInventors: Nei-Li Chan, Tsai-Kun Li, Chyuan-Chuan Wu, Ying-Ren Wang
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Publication number: 20130018180Abstract: Disclosed herein are a crystal of a human TOPII (hTOPII)-DNA binary complex, the method for preparing the same and the use thereof. The hTOPII-DNA binary complex includes an hTOPII portion that contains an hTOPII core domain (hTOPIIcore), and a synthetic double-stranded DNA in complex with the hTOPII portion. The synthetic double-stranded DNA has a first DNA strand comprising nucleotide positions 3 to 20 of the sequence of 5?-NNNCCGAGCNNNNGCTCGGNNN-3? (SEQ ID NO: 1), wherein N is any one of adenine, thymine, cytosine, or guanine, and a second DNA strand complementary to the first DNA strand.Type: ApplicationFiled: July 24, 2012Publication date: January 17, 2013Applicant: National Taiwan UniversityInventors: Nei-Li CHAN, Tsai-Kun Li, Chyuan-Chuan Wu, Ying-Ren Wang
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Patent number: 8218612Abstract: An effective data sequence based timing error detector (EDS-TED) for baseband transmission system using Tomlinson-Harashima Precoder is disclosed. The EDS-TED extracts timing error information embedded in the received signal to build up autocorrelation between the ESD signals and minimize the mean square error between the received and desired EDS so as to improve the performance of the TED in terms of Peak-to-Peak Jitter and TED gain. Thus the quality of the received signal increases and the error rate decreases.Type: GrantFiled: March 12, 2009Date of Patent: July 10, 2012Assignee: National Taiwan UniversityInventors: Ying-Ren Chien, Hen-Wai Tsao
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Patent number: 8089586Abstract: A display has color pixels that can be controlled to show color images. Differences in electric fields in different color pixels having color filters with different dielectric constants can be compensated by providing electrodes with different patterns for the different color pixels. For example, the electrodes can have slits in which the widths of the slits can be different for pixels having different colors.Type: GrantFiled: January 9, 2009Date of Patent: January 3, 2012Assignee: Chimei Innolux CorporationInventors: Chih-Yung Hsieh, Chien-Hong Chen, Ying-Ren Chen, Ju-Hsien Chen
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Publication number: 20110120411Abstract: An apparatus and method for varying a counter force to valve spring preload of a brake exhaust valve to undertake engine braking, includes a solenoid controlled hydraulic actuator. A control cylinder is arranged to move with a rocker arm and a control piston is arranged to slide within the control cylinder. During engine braking the control piston slides to press the valve stem to open the brake exhaust valve. An oil chamber is arranged above the control piston and is open into the control cylinder. A source of pressurized oil is selectably introduced into the oil chamber by the solenoid controlled hydraulic actuator to slide the control piston within the control cylinder to open and hold open the brake exhaust valve.Type: ApplicationFiled: November 23, 2009Publication date: May 26, 2011Applicant: International Engine Intellectual Property Company, LLCInventors: Ying Ren, Michale D. Bartkowicz, Qianfan Xin, Martin R. Zielke, Luis Carlos Cattani
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Patent number: 7750450Abstract: A system may include a first integrated circuit die comprising a first upper surface, an integrated circuit package substrate comprising a second upper surface, a wire coupled to the a first upper surface and to the second upper surface, a plurality of elements coupled to the first upper surface, and a second integrated circuit die coupled to the plurality of elements. A portion of the wire is disposed between the first integrated circuit die and the second integrated circuit die.Type: GrantFiled: December 20, 2006Date of Patent: July 6, 2010Assignee: Intel CorporationInventors: Ying-Ren Lin, Nelson Punzalan, Chee Key Chung
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Patent number: 7697844Abstract: The present disclosure provides a system and method for allocating bandwidth in remote equipment on a passive optical network (PON), wherein the system includes an optical line terminal (OLT), which monitors the acceptance of traffic requesting the PON remote equipment for service and configures through signaling control the parameters for the operation of classifying, shaping, and scheduling the traffic in the remote equipment, and a remote equipment which classifies, shapes, and schedules the accepted traffic based on the parameters configured by the OLT and allocates a proper bandwidth to the accepted traffic, and outputs the traffic in the scheduled order. The present disclosure helps ensure the bandwidth and delay requirements of individual traffic flows in the PON remote equipment are met and interaction between traffic of the same or different service class groups is eliminated.Type: GrantFiled: December 13, 2006Date of Patent: April 13, 2010Assignee: Huawei Technologies Co., Ltd.Inventors: Yong Guo, Ge Fan, Ying Ren, Yanjiao Hui, Hui Yu
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Publication number: 20100054318Abstract: An effective data sequence based timing error detector (EDS-TED) for baseband transmission system using Tomlinson-Harashima Precoder is disclosed. The EDS-TED extracts timing error information embedded in the received signal to build up autocorrelation between the ESD signals and minimize the mean square error between the received and desired EDS so as to improve the performance of the TED in terms of Peak-to-Peak Jitter and TED gain. Thus the quality of the received signal increases and the error rate decreases.Type: ApplicationFiled: March 12, 2009Publication date: March 4, 2010Inventors: Ying-Ren Chien, Hen-Wai Tsao
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Publication number: 20090180063Abstract: A display has color pixels that can be controlled to show color images. Differences in electric fields in different color pixels having color filters with different dielectric constants can be compensated by providing electrodes with different patterns for the different color pixels. For example, the electrodes can have slits in which the widths of the slits can be different for pixels having different colors.Type: ApplicationFiled: January 9, 2009Publication date: July 16, 2009Applicant: CHI MEI OPROELECTRONICS CORPORATIONInventors: Chih-Yung Hsieh, Chien-Hong Chen, Ying-Ren Chen, Ju-Hsien Chen
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Publication number: 20080092952Abstract: Provided is an integrated amorphous silicon double-junction solar cell curtain wall, comprising a plurality of photovoltaic curtain wall plates, each of which being encapsulated by a double-junction amorphous silicon solar cell chip with a glass substrate, a glass plate, a glue film, a junction box, a lead and a frame; and an electric control unit having a controller; wherein an output of the photovoltaic curtain wall plate is connected to the controller of the electric control unit. A double-junction double-layer solar cell top cell film layer and a bottom cell film layer are disposed on a glass substrate of the cell chip, each of the top cell film layer and the bottom cell film layer comprising a P-layer, an I-layer, and an N-layer; an I-layer of the top cell film layer is amorphous silicon; and an I-layer of the bottom cell film layer is amorphous silicon or amorphous germanium-silicon.Type: ApplicationFiled: October 23, 2007Publication date: April 24, 2008Inventors: Wukui CHEN, Ying REN, Xiaoquan LEI
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Patent number: 7348211Abstract: A method for fabricating semiconductor packages is proposed. A plurality of substrates each having a chip thereon are prepared. Each substrate has similar length and width to the predetermined length and width of the semiconductor package. A carrier having a plurality of openings is prepared. Each opening is larger in length and width than the substrate. The substrates are positioned in the corresponding openings, and gaps between the substrates and the carrier are sealed. A molding process is performed to form an encapsulant over each opening to encapsulate the chip. An area on the carrier covered by the encapsulant is larger in length and width than the opening. After performing a mold-releasing process, a plurality of the semiconductor packages are formed by a singulation process to cut along substantially edges of each substrate according to the predetermined size of the semiconductor package. A waste of substrate material is avoided.Type: GrantFiled: April 27, 2005Date of Patent: March 25, 2008Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Ying-Ren Lin, Ho-Yi Tsai, Chien-Ping Huang, Cheng-Hsu Hsiao
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Patent number: 7271483Abstract: A bump structure of a semiconductor package and a method for fabricating the same are provided. The bump structure is used to connect a semiconductor element to a carrier of the semiconductor package. The fabrication method primarily employs an electroplating process to form the bump structure including an under bump metallurgy (UBM) layer, at least one I-shaped conductive pillar, and a solder material. This allows fine-pitch electrical connection pads to be arranged in the semiconductor package, and also provides an enhanced support structure and a sufficient height between the semiconductor element and the carrier.Type: GrantFiled: December 29, 2004Date of Patent: September 18, 2007Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Ying-Ren Lin, Chien-Ping Huang, Ho-Yi Tsai, Cheng-Hsu Hsiao
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Publication number: 20070212071Abstract: The present disclosure provides a system and method for allocating bandwidth in remote equipment on a passive optical network (PON), wherein the system includes an optical line terminal (OLT), which monitors the acceptance of traffic requesting the PON remote equipment for service and configures through signaling control the parameters for the operation of classifying, shaping, and scheduling the traffic in the remote equipment, and a remote equipment which classifies, shapes, and schedules the accepted traffic based on the parameters configured by the OLT and allocates a proper bandwidth to the accepted traffic, and outputs the traffic in the scheduled order. The present disclosure helps ensure the bandwidth and delay requirements of individual traffic flows in the PON remote equipment are met and interaction between traffic of the same or different service class groups is eliminated.Type: ApplicationFiled: December 13, 2006Publication date: September 13, 2007Applicant: Huawei Tecnologies Co., Ltd.Inventors: Yong Guo, Ge Fan, Ying Ren, Yanjiao Hui, Hui Yu
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Publication number: 20070141761Abstract: A method for fabricating semiconductor packages includes the steps of: providing a plurality of substrates and a carrier having a plurality of openings, wherein, each of the substrates has at least one chip (die) disposed thereon, length and width of the substrates are approximately equal to the predefined length and width of semiconductor packages, and length and width of the openings of the carrier are bigger than length and width of the substrates; respectively positioning the substrates in the openings of the carrier and blocking the gaps between the substrates and the carrier so as to prevent the gaps from penetrating through the carrier; performing a mold press process so as to form an encapsulant on each of the openings for encapsulating the chip, wherein length and width of the area covered by the encapsulant are bigger than length and width of the opening; performing a mold releasing process; and cutting along edges of the substrates according to the predefined length and width of semiconductor packaType: ApplicationFiled: February 6, 2007Publication date: June 21, 2007Applicant: Siliconware Precision Industries Co., Ltd.Inventors: Ying-Ren Lin, Ho-Yi Tsai, Chien-Ping Huang, Cheng-Hsu Hsiao
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Publication number: 20070054484Abstract: A method for positioning a semiconductor component is disclosed. The method includes providing the semiconductor component and a carrier, the carrier having a plurality of openings, a protruded portion being provided at each corner position of each of the openings and extended toward a center of the opening, a distance between two diagonal protruded portions of the opening being slightly larger than that between two diagonal corners of the semiconductor component; and positioning the semiconductor component in the openings of the carrier via the protruded portions provided at each corner position of each of the openings.Type: ApplicationFiled: October 26, 2006Publication date: March 8, 2007Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Ying-Ren Lin, Ho-Yi Tsai, Chien-Ping Huang
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Patent number: 7180183Abstract: A semiconductor device with reinforced under-support structure and a method for fabricating the semiconductor device are provided, which can be used in the packaging of an MPBGA/TFBGA (Multi-Package Ball Grid Array & Thin Fine-pitch Ball Grid Array) module to help reinforce the TFBGA under-support structure therein. The proposed chip-packaging method is characterized by the provision of large-area solder pads at the corners of a solder-pad array used for TFBGA attaching application, in order to form solder bumps of a large cross section and volume during reflow process to help reinforce the TFBGA under-package structure. This feature can reinforce the TFBGA under-package structure without having to use flip-chip underfill technology, and without having to use extra large type solder balls and arrange pads into different pitches as in the prior art.Type: GrantFiled: May 19, 2003Date of Patent: February 20, 2007Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Ho-Yi Tsai, Chin-Ming Shih, Ying-Ren Lin
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Patent number: 7173828Abstract: A ground pad structure for preventing solder extrusion and a semiconductor package having the ground pad structure are disclosed, wherein the ground pad structure has the ground pads located along the circumference of its ground plane be formed in a non-solder mask defined manner. Accordingly, a good grounding quality is maintained, and the occurrence of the electrical bridging among the adjacent conductive traces can be avoided as the extrusion of the molten solder bumps from the ground pads located along the ground pad structure's circumference toward their adjacent conductive traces is effectively prevented.Type: GrantFiled: September 29, 2003Date of Patent: February 6, 2007Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Ying-Ren Lin, Chih-Ming Huang, Ho-Yi Tsai
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Patent number: 7129119Abstract: A method for fabricating semiconductor packages is proposed. A plurality of substrates are prepared each having a chip thereon. Length and width of each substrate are equal to predetermined length and width of the semiconductor package. A carrier having a plurality of openings is prepared. A protruded portion is formed at each corner of each opening, wherein a distance between two diagonal protruded portions is slightly larger than that between two diagonal corners of the substrate. The substrates are fixed in the openings of the carrier by means of the protruded portions, and gaps between the substrates and the carrier are sealed. An encapsulant is formed over each opening to encapsulate the corresponding chip by a molding process. An area on the carrier covered by the encapsulant is larger in length and width than the opening. A plurality of the semiconductor packages are formed after performing mold-releasing and singulation processes.Type: GrantFiled: February 1, 2005Date of Patent: October 31, 2006Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Ying-Ren Lin, Ho-Yi Tsai, Chien-Ping Huang
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Publication number: 20060051954Abstract: A bump structure of a semiconductor package and a method for fabricating the same are provided. The bump structure is used to connect a semiconductor element to a carrier of the semiconductor package. The fabrication method primarily employs an electroplating process to form the bump structure including an under bump metallurgy (UBM) layer, at least one I-shaped conductive pillar, and a solder material. This allows fine-pitch electrical connection pads to be arranged in the semiconductor package, and also provides an enhanced support structure and a sufficient height between the semiconductor element and the carrier.Type: ApplicationFiled: December 29, 2004Publication date: March 9, 2006Applicant: Siliconware Precision Industries Co, Ltd.Inventors: Ying-Ren Lin, Chien-Ping Huang, Ho-Yi Tsai, Cheng-Hsu Hsiao
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Publication number: 20050287707Abstract: A method for fabricating semiconductor packages is proposed. A plurality of substrates each having a chip thereon are prepared. Each substrate has similar length and width to the predetermined length and width of the semiconductor package. A carrier having a plurality of openings is prepared. Each opening is larger in length and width than the substrate. The substrates are positioned in the corresponding openings, and gaps between the substrates and the carrier are sealed. A molding process is performed to form an encapsulant over each opening to encapsulate the chip. An area on the carrier covered by the encapsulant is larger in length and width than the opening. After performing a mold-releasing process, a plurality of the semiconductor packages are formed by a singulation process to cut along substantially edges of each substrate according to the predetermined size of the semiconductor package. A waste of substrate material is avoided.Type: ApplicationFiled: April 27, 2005Publication date: December 29, 2005Applicant: Siliconware Precision Industries Co., Ltd.Inventors: Ying-Ren Lin, Ho-Yi Tsai, Chien-Ping Huang, Cheng-Hsu Hsiao