Abstract: An electronic apparatus includes a processing unit, a buffer memory and a buffer manager. The buffer memory includes some packet buffer slots. Each of the packet buffer slots aligns to a packet size. The buffer manager includes a cache for registering available pointers. Each of the available pointers is configured to mark a start address of one of the packet buffer slots. The buffer manager is configured to monitor an available pointer count of the available pointers. When the processing unit transmits an allocation request to the buffer manager and the available count is enough, the buffer manager obtains one available pointer from the cache and integrates the one available pointer and the available pointer count into an allocation response, which is sent to the processing unit.