Patents by Inventor Ying-Shiou Lin
Ying-Shiou Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240105844Abstract: A native NMOS device includes: a P-type epitaxial layer, a first and a second insulation region, a first P-type well, a second P-type well, a gate, an N-type source, and an N-type drain. The P-type epitaxial layer has a first concentration of P-type doped impurities. The first P-type well completely encompasses and is in contact with a lower surface of the N-type source. The second P-type well completely encompasses and is in contact with a lower surface of the N-type drain. Each of the first P-type well and the second P-type well has a second concentration of P-type doped impurities, and the second concentration of P-type doped impurities is higher than the first concentration of P-type doped impurities. The second concentration of P-type doped impurities is sufficient for preventing a leakage current from flowing between the N-type drain and the P-type substrate while the native NMOS device is in operation.Type: ApplicationFiled: September 7, 2023Publication date: March 28, 2024Inventors: Ying-Shiou Lin, Wu-Te Weng, Yong-Zhong Hu
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Publication number: 20220165880Abstract: A high voltage device includes: a semiconductor layer, a well, a body region, a gate, a source, a drain, and a drift oxide region. The semiconductor layer is formed on a substrate, wherein the semiconductor layer has at least one trench. The well is formed in the semicoducotor layer. The body region is formed in the well. The gate is formed on the well, and is in contact with the well. The source and the drain are located below, outside, and at different sides of the gate, in the body region and the well respectively. The drift oxide region is formed on a drift region, wherein a bottom surface of the drift oxide region is higher than a bottom surface of the trench.Type: ApplicationFiled: February 7, 2022Publication date: May 26, 2022Inventors: Tsung-Yi Huang, Kun-Huang Yu, Ying-Shiou Lin, Chu-Feng Chen, Chung-Yu Hung, Yi-Rong Tu
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Publication number: 20200111906Abstract: A high voltage device includes: a semiconductor layer, a well, a body region, a gate, a source, a drain, and a drift oxide region. The semiconductor layer is formed on a substrate, wherein the semiconductor layer has at least one trench. The well is formed in the semiconductor layer. The body region is formed in the well. The gate is formed on the well, and is in contact with the well. The source and the drain are located below, outside, and at different sides of the gate, in the body region and the well respectively. The drift oxide region is formed on a drift region, wherein a bottom surface of the drift oxide region is higher than a bottom surface of the trench.Type: ApplicationFiled: August 13, 2019Publication date: April 9, 2020Inventors: Tsung-Yi Huang, Kun-Huang Yu, Ying-Shiou Lin, Chu-Feng Chen, Chung-Yu Hung, Yi-Rong Tu
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Patent number: 10355088Abstract: The present invention provides a MOS (Metal-Oxide-Silicon) device having mitigated threshold voltage roll-off and a threshold voltage roll-off mitigation method therefor. The MOS device includes: a substrate, a well region, an isolation region, a gate, two LDDs (Lightly-Doped-Drains), a source, a drain and a compensation doped region. The compensation doped region is substantially in contact with at least a part of a recessed portion along the channel length direction. Viewing from a cross-section view, at a boundary where the compensation doped region is in contact with the isolation region along the channel length direction, the compensation doped region has two doped region widths along the channel width direction, wherein, the two doped region widths of the compensation doped region are both not greater than 10% of the width of the operation region. Two doped region widths are defined as distances within an interior part and an exterior part of the operation region, respectively.Type: GrantFiled: June 14, 2017Date of Patent: July 16, 2019Assignee: RICHTEK TECHNOLOGY CORPORATIONInventors: Tsung-Yi Huang, Ying-Shiou Lin
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Publication number: 20180190773Abstract: The present invention provides a MOS (Metal-Oxide-Silicon) device having mitigated threshold voltage roll-off and a threshold voltage roll-off mitigation method therefor. The MOS device includes: a substrate, a well region, an isolation region, a gate, two LDDs (Lightly-Doped-Drains), a source, a drain and a compensation doped region. The compensation doped region is substantially in contact with at least a part of a recessed portion along the channel length direction. Viewing from a cross-section view, at a boundary where the compensation doped region is in contact with the isolation region along the channel length direction, the compensation doped region has two doped region widths along the channel width direction, wherein, the two doped region widths of the compensation doped region are both not greater than 10% of the width of the operation region. Two doped region widths are defined as distances within an interior part and an exterior part of the operation region, respectively.Type: ApplicationFiled: June 14, 2017Publication date: July 5, 2018Inventors: Tsung-Yi Huang, Ying-Shiou Lin
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Patent number: 8710633Abstract: The present invention discloses a semiconductor overlapped PN structure and manufacturing method thereof. The method includes: providing a substrate; providing a first mask to define a P (or N) type well and at least one overlapped region in the substrate; implanting P (or N) type impurities into the P (or N) type well and the at least one overlapped region; providing a second mask having at least one opening to define an N (or P) type well in the substrate, and to define at least one dual-implanted region in the at least one overlapped region; implanting N (or P) type impurities into the N (or P) type well and the at least one dual-implanted region such that the at least one dual-implanted region has P type and N type impurities.Type: GrantFiled: April 16, 2013Date of Patent: April 29, 2014Assignee: Richtek Technology CorporationInventors: Tsung-Yi Huang, Chien-Hao Huang, Ying-Shiou Lin
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Publication number: 20130256846Abstract: The present invention discloses a semiconductor overlapped PN structure and manufacturing method thereof. The method includes: providing a substrate; providing a first mask to define a P (or N) type well and at least one overlapped region in the substrate; implanting P (or N) type impurities into the P (or N) type well and the at least one overlapped region; providing a second mask having at least one opening to define an N (or P) type well in the substrate, and to define at least one dual-implanted region in the at least one overlapped region; implanting N (or P) type impurities into the N (or P) type well and the at least one dual-implanted region such that the at least one dual-implanted region has P type and N type impurities.Type: ApplicationFiled: April 16, 2013Publication date: October 3, 2013Applicant: RICHTEK TECHNOLOGY CORPORATIONInventors: Tsung-Yi Huang, Chien-Hao Huang, Ying-Shiou Lin
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Patent number: 8524586Abstract: The present invention discloses a semiconductor overlapped PN structure and manufacturing method thereof. The method includes: providing a substrate; providing a first mask to define a P (or N) type well and at least one overlapped region in the substrate; implanting P (or N) type impurities into the P (or N) type well and the at least one overlapped region; providing a second mask having at least one opening to define an N (or P) type well in the substrate, and to define at least one dual-implanted region in the at least one overlapped region; implanting N (or P) type impurities into the N (or P) type well and the at least one dual-implanted region such that the at least one dual-implanted region has P type and N type impurities.Type: GrantFiled: April 20, 2011Date of Patent: September 3, 2013Assignee: Richtek Technology CorporationInventors: Tsung-Yi Huang, Chien-Hao Huang, Ying-Shiou Lin
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Patent number: 8525258Abstract: The present invention discloses a method for controlling the impurity density distribution in semiconductor device and a semiconductor device made thereby. The control method includes the steps of: providing a substrate; defining a doped area which includes at least one first region; partially masking the first region by a mask pattern; and doping impurities in the doped area to form one integrated doped region in the first region, whereby the impurity concentration of the first region is lower than a case where the first region is not masked by the mask pattern.Type: GrantFiled: June 17, 2010Date of Patent: September 3, 2013Assignee: Richtek Technology Corporation, R.O.C.Inventors: Tsung-Yi Huang, Ying-Shiou Lin
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Patent number: 8354718Abstract: An apparatus comprising a substrate of first dopant type and first dopant concentration; pocket regions in the substrate and having the first dopant type and a second dopant concentration greater than the first dopant concentration; a gate stack over the substrate and laterally between the pocket regions; first and second source/drain regions on opposing sides of the gate stack and vertically between the gate stack and the pocket regions, the first and second source/drain regions having a second dopant type opposite the first dopant type and a third dopant concentration; and third and fourth source/drain regions having the second dopant type and a fourth dopant concentration that is greater than the third dopant concentration, wherein the pocket regions are between the third and fourth source/drain regions, and the third and fourth source/drain regions are vertically between the first and second source/drain regions and a bulk portion of the substrate.Type: GrantFiled: May 22, 2007Date of Patent: January 15, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Chiang Wang, Yi-Ming Sheu, Ying-Shiou Lin
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Publication number: 20120267767Abstract: The present invention discloses a semiconductor overlapped PN structure and manufacturing method thereof. The method includes: providing a substrate; providing a first mask to define a P (or N) type well and at least one overlapped region in the substrate; implanting P (or N) type impurities into the P (or N) type well and the at least one overlapped region; providing a second mask having at least one opening to define an N (or P) type well in the substrate, and to define at least one dual-implanted region in the at least one overlapped region; implanting N (or P) type impurities into the N (or P) type well and the at least one dual-implanted region such that the at least one dual-implanted region has P type and N type impurities.Type: ApplicationFiled: April 20, 2011Publication date: October 25, 2012Inventors: TSUNG-YI HUANG, Chien-Hao Huang, Ying-Shiou Lin
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Publication number: 20120217579Abstract: The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device includes: a substrate, having a P (or N) type well and an isolation structure for defining a device region; a drift region, located in the device region, having a first region and a second region wherein the first region is an N (or P) type region, and the second region is a P (or N) type region or an N (or P) type region with different dopant concentration from the first region, and from top view, the first region and the second region include sub-regions distributed in the drift region; an N (or P) type source and drain; and a gate on a surface of the substrate, between the source and drain in the device region.Type: ApplicationFiled: August 8, 2011Publication date: August 30, 2012Inventors: Tsung-Yi Huang, Ying-Shiou Lin
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Patent number: 8143680Abstract: A gated-diode semiconductor device or similar component and a method of fabricating the device. The device features a gate structure disposed on a substrate over a channel and adjacent a source and a drain. The top of the source or drain region, or both, are formed so as to be at a higher elevation, in whole or in part, than the bottom of the gate structure. This configuration may be achieved by overlaying the gate structure and substrate with a profile layer that guides a subsequent etch process to create a sloped profile. The source and drain, if both are present, may be symmetrical or asymmetrical. This configuration significantly reduces dopant encroachment and, as a consequence, reduces junction leakage.Type: GrantFiled: May 12, 2010Date of Patent: March 27, 2012Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Da-Wen Lin, Ying-Shiou Lin, Shyh-Wei Wang, Li-Ping Huang, Ying-Keung Leung, Carlos H. Diaz
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Publication number: 20110309443Abstract: The present invention discloses a method for controlling the impurity density distribution in semiconductor device and a semiconductor device made thereby. The control method includes the steps of: providing a substrate; defining a doped area which includes at least one first region; partially masking the first region by a mask pattern; and doping impurities in the doped area to form one integrated doped region in the first region, whereby the impurity concentration of the first region is lower than a case where the first region is not masked by the mask pattern.Type: ApplicationFiled: June 17, 2010Publication date: December 22, 2011Inventors: Tsung-Yi Huang, Ying-Shiou Lin
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Publication number: 20100237441Abstract: A gated-diode semiconductor device or similar component and a method of fabricating the device. The device features a gate structure disposed on a substrate over a channel and adjacent a source and a drain. The top of the source or drain region, or both, are formed so as to be at a higher elevation, in whole or in part, than the bottom of the gate structure. This configuration may be achieved by overlaying the gate structure and substrate with a profile layer that guides a subsequent etch process to create a sloped profile. The source and drain, if both are present, may be symmetrical or asymmetrical. This configuration significantly reduces dopant encroachment and, as a consequence, reduces junction leakage.Type: ApplicationFiled: May 12, 2010Publication date: September 23, 2010Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Da-Wen Lin, Ying-Shiou Lin, Shyh-Wei Wang, Li-Ping Huang, Ying-Keung Leung, Carlis H. Diaz
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Patent number: 7732877Abstract: A gated-diode semiconductor device or similar component and a method of fabricating the device. The device features a gate structure disposed on a substrate over a channel and adjacent a source and a drain. The top of the source or drain region, or both, are formed so as to be at a higher elevation, in whole or in part, than the bottom of the gate structure. This configuration may be achieved by overlaying the gate structure and substrate with a profile layer that guides a subsequent etch process to create a sloped profile. The source and drain, if both are present, may be symmetrical or asymmetrical. This configuration significantly reduces dopant encroachment and, as a consequence, reduces junction leakage.Type: GrantFiled: April 2, 2007Date of Patent: June 8, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Da-Wen Lin, Ying-Shiou Lin, Shyh-Wei Wang, Li-Ping Huang, Ying-Keung Leung, Carlos H. Diaz
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Publication number: 20080290412Abstract: An apparatus comprising a substrate of first dopant type and first dopant concentration; pocket regions in the substrate and having the first dopant type and a second dopant concentration greater than the first dopant concentration; a gate stack over the substrate and laterally between the pocket regions; first and second source/drain regions on opposing sides of the gate stack and vertically between the gate stack and the pocket regions, the first and second source/drain regions having a second dopant type opposite the first dopant type and a third dopant concentration; and third and fourth source/drain regions having the second dopant type and a fourth dopant concentration that is greater than the third dopant concentration, wherein the pocket regions are between the third and fourth source/drain regions, and the third and fourth source/drain regions are vertically between the first and second source/drain regions and a bulk portion of the substrate.Type: ApplicationFiled: May 22, 2007Publication date: November 27, 2008Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Chiang Wang, Yi-Ming Sheu, Ying-Shiou Lin
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Publication number: 20080237746Abstract: A gated-diode semiconductor device or similar component and a method of fabricating the device. The device features a gate structure disposed on a substrate over a channel and adjacent a source and a drain. The top of the source or drain region, or both, are formed so as to be at a higher elevation, in whole or in part, than the bottom of the gate structure. This configuration may be achieved by overlaying the gate structure and substrate with a profile layer that guides a subsequent etch process to create a sloped profile. The source and drain, if both are present, may be symmetrical or asymmetrical. This configuration significantly reduces dopant encroachment and, as a consequence, reduces junction leakage.Type: ApplicationFiled: April 2, 2007Publication date: October 2, 2008Inventors: Da-Wen Lin, Ying-Shiou Lin, Shyh-Wei Wang, Li-Ping Huang, Ying-Keung Leung, Carlos H. Diaz