Abstract: An integrated circuit device including a substrate, a gate structure formed over the substrate, a channel formed in the substrate under the gate, a lightly-doped drain-side LDD region formed in the substrate adjacent to a drain-side of the channel (preferably by a LATID process), a drain region formed in the substrate near to the drain-side LDD region, and a drain-side DDD region substantially separating the drain-side LDD region from the drain region. Preferably, the integrated circuit device is symmetrically formed such that a lightly-doped source-side LDD region is formed in the substrate adjacent to a source-side of the channel (again preferably by a LATID process), a source region is formed in the substrate near to the source-side LDD region, and a source-side DDD region is formed in the substrate to substantially separate the source-side LDD region from the source region. Further preferably, the DDD regions substantially isolate the source and drain from a bulk portion of the substrate.

Abstract: An integrated circuit device including a substrate, a gate structure formed over the substrate, a channel formed in the substrate under the gate, a lightly-doped drain-side LDD region formed in the substrate adjacent to a drain-side of the channel (preferably by a LATID process), a drain region formed in the substrate near to the drain-side LDD region, and a drain-side DDD region substantially separating the drain-side LDD region from the drain region. Preferably, the integrated circuit device is symmetrically formed such that a lightly-doped source-side LDD region is formed in the substrate adjacent to a source-side of the channel (again preferably by a LATID process), a source region is formed in the substrate near to the source-side LDD region, and a source-side DDD region is formed in the substrate to substantially separate the source-side LDD region from the source region. Further preferably, the DDD regions substantially isolate the source and drain from a bulk portion of the substrate.

Abstract: In a method for producing an auxiliary gate lightly doped drain structure, a gate region is placed on a substrate between two source/drain regions. A first implant of atoms is made into the substrate on two sides of the gate region. Sidewalls are formed on the two sides of the gate region. Auxiliary gate regions are formed over the sidewalls. The auxiliary gate regions are separated from the gate region by the sidewalls. Dielectric regions are formed over the auxiliary gate regions. A second implant of atoms is performed into the substrate on two sides of the dielectric regions. The sidewalls and the auxiliary gate regions are composed of resistive material.

Abstract: In a method for producing a transistor with an overlapping gate region, a gate region is placed on a substrate between two source/drain regions. Spacers are placed around the gate region. The spacers are formed of dielectric material. A thin layer of polysilicon is deposited over the two source/drain regions and over electrically insulating regions adjacent to the two source/drain regions. Portions of the thin layer of polysilicon are oxidized to electrically isolate the two source/drain regions. A metal-silicide layer is formed on the portions of the thin layer of polysilicon which are not oxidized. The metal-silicide layer is connected to a metal layer. The electrical contact of the metal-silicide layer and the metal layer is over an electrically insulating layer.

Abstract: A method produces a transistor with an overlapping gate. A first gate region is placed on a substrate between two source/drain regions. The first gate region includes a polysilicon region on top of a dielectric region. Gate overlap regions are placed around the polysilicon region. The gate overlap regions extend out over the two source/drain regions. The gate overlap regions are formed of a metal-silicide layer, for example Titanium-silicide. A top portion of the metal-silicide layer is oxidized to form a silicon dioxide layer on top of the metal-silicide layer. At the time of oxidation, the metal-silicide layer is also annealed to which further helps to improves the Titanium-silicide stoichiometry.

Abstract: For a structure with an overlapping gate region, a first insulator layer is placed on a substrate. A source/drain polysilicon layer is placed on the insulator layer. The source/drain polysilicon layer is doped with atoms of a first conductivity type. A second insulator layer is placed on the source/drain polysilicon layer. A gap is etched in the second insulator layer and the source/drain polysilicon layer to expose a portion of the first insulator layer. The exposed portion of the first insulator layer and an additional amount of the first insulator layer under the second insulator is etched so as to enlarge the gap and to undercut a portion of the source/drain polysilicon layer. Two polysilicon filler regions are formed which fill a portion of the gap including the undercut area under the source/drain polysilicon layer. A gate polysilicon region is formed in the gap and extends over the source/drain polysilicon layer.