Patents by Inventor Ying Ting Hsia

Ying Ting Hsia has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200393642
    Abstract: An optical element driving mechanism is provided and includes a fixed assembly, a movable assembly, a driving assembly and a stopping assembly. The fixed assembly has a main axis. The movable assembly is configured to connect an optical element, and the movable assembly is movable relative to the fixed assembly. The driving assembly is configured to drive the movable assembly to move relative to the fixed assembly. The stopping assembly is configured to limit the movement of the movable assembly relative to the fixed assembly within a range of motion.
    Type: Application
    Filed: June 12, 2020
    Publication date: December 17, 2020
    Inventors: Chao-Chang HU, Liang-Ting HO, Chen-Er HSU, Yi-Liang CHAN, Fu-Lai TSENG, Fu-Yuan WU, Chen-Chi KUO, Ying-Jen WANG, Wei-Han HSIA, Yi-Hsin TSENG, Wen-Chang LIN, Chun-Chia LIAO, Shou-Jen LIU, Chao-Chun CHANG, Yi-Chieh LIN, Shang-Yu HSU, Yu-Huai LIAO, Shih-Wei HUNG, Sin-Hong LIN, Kun-Shih LIN, Yu-Cheng LIN, Wen-Yen HUANG, Wei-Jhe SHEN, Chih-Shiang WU, Sin-Jhong SONG, Che-Hsiang CHIU, Sheng-Chang LIN
  • Patent number: 10804149
    Abstract: A method includes forming a bottom source/drain contact plug in a bottom inter-layer dielectric. The bottom source/drain contact plug is electrically coupled to a source/drain region of a transistor. The method further includes forming an inter-layer dielectric overlying the bottom source/drain contact plug. A source/drain contact opening is formed in the inter-layer dielectric, with the bottom source/drain contact plug exposed through the source/drain contact opening. A dielectric spacer layer is formed to have a first portion extending into the source/drain contact opening and a second portion over the inter-layer dielectric. An anisotropic etching is performed on the dielectric spacer layer, and a remaining vertical portion of the dielectric spacer layer forms a source/drain contact spacer. The remaining portion of the source/drain contact opening is filled to form an upper source/drain contact plug.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: October 13, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Tsang Hsieh, Cha-Hsin Chao, Yi-Wei Chiu, Li-Te Hsu, Ying Ting Hsia
  • Publication number: 20200303255
    Abstract: A method for forming semiconductor device structure is provided. The method includes forming a gate stack over a semiconductor substrate and forming a spacer element over a sidewall of the gate stack. The method also includes forming a dielectric layer over the semiconductor substrate to surround the gate stack and the spacer element and replacing the gate stack with a metal gate stack. The method further includes forming a protection element over the metal gate stack and forming a conductive contact partially surrounded by the dielectric layer. A portion of the conductive contact is formed directly above a portion of the protection element.
    Type: Application
    Filed: June 3, 2020
    Publication date: September 24, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hua-Li HUNG, Chih-Lun LU, Hsu-Yu HUANG, Tsung-Fan YIN, Ying-Ting HSIA, Yi-Wei CHIU, Li-Te HSU
  • Publication number: 20200286781
    Abstract: A method of forming a semiconductor device includes forming a source/drain region on a substrate and forming a first interlayer dielectric (ILD) layer over the source/drain region. The method further includes forming a second ILD layer over the first ILD layer, forming a source/drain contact structure within the first ILD layer and the second ILD layer, and selectively removing a portion of the source/drain contact structure to form a concave top surface of the source/drain contact structure.
    Type: Application
    Filed: May 26, 2020
    Publication date: September 10, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yun-Yu HSIEH, Jeng Chang HER, Cha-Hsin CHAO, Yi-Wei CHIU, Li-Te HSU, Ying Ting HSIA
  • Publication number: 20200243378
    Abstract: In a method for manufacturing a semiconductor device, a first interlayer dielectric layer is formed over a substrate. First recesses are formed in the first interlayer dielectric layer. First metal wirings are formed in the first recesses. A first etch-resistance layer is formed in a surface of the first interlayer dielectric layer between the first metal wirings but not on upper surfaces of the first metal wirings. A first insulating layer is formed on the first etch-resistance layer and the upper surfaces of the first metal wirings.
    Type: Application
    Filed: April 10, 2020
    Publication date: July 30, 2020
    Inventors: Jeng Chang Her, Cha-Hsin Chao, Yi-Wei Chiu, Li-Te Hsu, Ying Ting Hsia
  • Patent number: 10692762
    Abstract: A semiconductor device is provided. The semiconductor device includes a gate stack over a semiconductor substrate and a spacer element over a sidewall of the gate stack. The spacer element has a lower portion and an upper portion, the lower portion has a substantially uniform width. The upper portion becomes wider along a direction from a top of the spacer element towards the lower portion, and a bottom of the upper portion is higher than a top of the gate stack. The semiconductor device also includes a dielectric layer surrounding the gate stack and the spacer element. The semiconductor device further includes a conductive contact penetrating through the dielectric layer and electrically connected to a conductive feature over the semiconductor substrate.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: June 23, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hua-Li Hung, Chih-Lun Lu, Hsu-Yu Huang, Tsung-Fan Yin, Ying-Ting Hsia, Yi-Wei Chiu, Li-Te Hsu
  • Patent number: 10679896
    Abstract: A method of forming a semiconductor device includes forming a source/drain region on a substrate and forming a first interlayer dielectric (ILD) layer over the source/drain region. The method further includes forming a first conductive region within the first ILD layer, selectively removing a portion of the first conductive region to form a concave top surface of the first conductive region. The method also includes forming a second ILD layer over the first ILD layer and forming a second conductive region within the second ILD layer and on the concave top surface. The concave top surface provides a large contact area, and hence reduced contact resistance between the first and second conductive regions.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: June 9, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yun-Yu Hsieh, Jeng Chang Her, Cha-Hsin Chao, Yi-Wei Chiu, Li-Te Hsu, Ying Ting Hsia
  • Patent number: 10651079
    Abstract: In a method for manufacturing a semiconductor device, a first interlayer dielectric layer is formed over a substrate. First recesses are formed in the first interlayer dielectric layer. First metal wirings are formed in the first recesses. A first etch-resistance layer is formed in a surface of the first interlayer dielectric layer between the first metal wirings but not on upper surfaces of the first metal wirings. A first insulating layer is formed on the first etch-resistance layer and the upper surfaces of the first metal wirings.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: May 12, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTUING CO., LTD.
    Inventors: Jeng Chang Her, Cha-Hsin Chao, Yi-Wei Chiu, Li-Te Hsu, Ying Ting Hsia
  • Publication number: 20200127093
    Abstract: A method for manufacturing a semiconductor device includes following operations. A semiconductor substrate is received. A first semiconductive layer is formed over the semiconductor substrate. A plurality of dopants is formed in a first portion of the first semiconductive layer. A second portion of the first semiconductive layer is removed to form a patterned first semiconductive layer. A first sidewall profile of the first portion after the removing of the second portion of the first semiconductive layer is controlled by adjusting a distribution of the plurality of dopants in the first portion. An underneath layer is patterned to form a hole in the underneath layer using the patterned first semiconductive layer as a mask to pattern. A sidewall profile of the hole in the underneath layer is controlled by the first sidewall profile of the first portion of the first semiconductive layer.
    Type: Application
    Filed: December 17, 2019
    Publication date: April 23, 2020
    Inventors: I-HSIU WANG, YEAN-ZHAW CHEN, YING-TING HSIA, JHAO-PING JIANG, CHUN-CHIH CHENG
  • Patent number: 10522408
    Abstract: A FinFET device and a method of forming the same are provided. A method includes forming a fin over a substrate. An isolation region is formed adjacent the fin. A dummy gate structure is formed over the fin. The fin adjacent the dummy gate structure is recessed to form a first recess. The first recess has a U-shaped bottom surface. The U-shaped bottom surface is below a top surface of the isolation region. The first recess is reshaped to form a reshaped first recess. The reshaped first recess has a V-shaped bottom surface. At least a portion of the V-shaped bottom surface comprises one or more steps. A source/drain region is epitaxially grown in the reshaped first recess.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: December 31, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Teng Liao, Chih-Shan Chen, Yi-Wei Chiu, Ying Ting Hsia, Tzu-Chan Weng
  • Patent number: 10510598
    Abstract: A method includes forming a bottom source/drain contact plug in a bottom inter-layer dielectric. The bottom source/drain contact plug is electrically coupled to a source/drain region of a transistor. The method further includes forming an inter-layer dielectric overlying the bottom source/drain contact plug. A source/drain contact opening is formed in the inter-layer dielectric, with the bottom source/drain contact plug exposed through the source/drain contact opening. A dielectric spacer layer is formed to have a first portion extending into the source/drain contact opening and a second portion over the inter-layer dielectric. An anisotropic etching is performed on the dielectric spacer layer, and a remaining vertical portion of the dielectric spacer layer forms a source/drain contact spacer. The remaining portion of the source/drain contact opening is filled to form an upper source/drain contact plug.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Tsang Hsieh, Cha-Hsin Chao, Yi-Wei Chiu, Li-Te Hsu, Ying Ting Hsia
  • Patent number: 10510839
    Abstract: A method for manufacturing a semiconductor device includes following operations. A semiconductor substrate is received. A first semiconductive layer over the semiconductor substrate is formed. A plurality of dopants are formed in a first portion of the first semiconductive layer. A second portion of the first semiconductive layer is removed to form a patterned first semiconductive layer. A first sidewall profile of the first portion after the removing the second portion of the first semiconductive layer is controlled by adjusting a distribution of the plurality of dopants in the first portion.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: December 17, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: I-Hsiu Wang, Yean-Zhaw Chen, Ying-Ting Hsia, Jhao-Ping Jiang, Chun-Chih Cheng
  • Publication number: 20190245055
    Abstract: A method of forming a gate structure includes forming an opening through an insulating layer and forming a first work function metal layer in the opening. The method also includes recessing the first work function metal layer into the opening to form a recessed first work function metal layer, and forming a second work function metal layer in the opening and over the first work function metal layer. The second work function metal layer lines and overhangs the recessed first work function metal layer.
    Type: Application
    Filed: April 22, 2019
    Publication date: August 8, 2019
    Inventors: Yi-Chun Chen, Tsung Fan Yin, Li-Te Hsu, Ying Ting Hsia, Yi-Wei Chiu
  • Publication number: 20190165101
    Abstract: A method for manufacturing a semiconductor device includes following operations. A semiconductor substrate is received. A first semiconductive layer over the semiconductor substrate is formed. A plurality of dopants are formed in a first portion of the first semiconductive layer. A second portion of the first semiconductive layer is removed to form a patterned first semiconductive layer. A first sidewall profile of the first portion after the removing the second portion of the first semiconductive layer is controlled by adjusting a distribution of the plurality of dopants in the first portion.
    Type: Application
    Filed: July 24, 2018
    Publication date: May 30, 2019
    Inventors: I-HSIU WANG, YEAN-ZHAW CHEN, YING-TING HSIA, JHAO-PING JIANG, CHUN-CHIH CHENG
  • Publication number: 20190148181
    Abstract: The present disclosure relates to an apparatus for wafer cleaning. The apparatus includes an enclosure made of a noncombustible material, a wafer holder, a cleaning nozzle, at least one sensor, and an exhaust unit. The wafer holder can hold and heat a wafer. The cleaning nozzle can supply a flow of a cleaning fluid onto a surface of the wafer. The at least one sensor can detect attributes of the wafer. The exhaust unit can expel a vapor generated by the cleaning fluid in the enclosure. The exhaust unit can include a rinse nozzle to rinse the vapor passing through the exhaust unit with a mist.
    Type: Application
    Filed: August 10, 2018
    Publication date: May 16, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jieh-Chau HUANG, Bi-Ming YEN, Hung-Lung HU, Ying Ting HSIA, Ping-Jung HUANG, Pei Yen HSIA
  • Publication number: 20190139822
    Abstract: In a method for manufacturing a semiconductor device, a first interlayer dielectric layer is formed over a substrate. First recesses are formed in the first interlayer dielectric layer. First metal wirings are formed in the first recesses. A first etch-resistance layer is formed in a surface of the first interlayer dielectric layer between the first metal wirings but not on upper surfaces of the first metal wirings. A first insulating layer is formed on the first etch-resistance layer and the upper surfaces of the first metal wirings.
    Type: Application
    Filed: December 17, 2018
    Publication date: May 9, 2019
    Inventors: Jeng Chang HER, Cha-Hsin CHAO, Yi-Wei CHIU, Li-Te HSU, Ying Ting HSIA
  • Publication number: 20190131176
    Abstract: A FinFET device and a method of forming the same are provided. A method includes forming a fin over a substrate. An isolation region is formed adjacent the fin. A dummy gate structure is formed over the fin. The fin adjacent the dummy gate structure is recessed to form a first recess. The first recess has a U-shaped bottom surface. The U-shaped bottom surface is below a top surface of the isolation region. The first recess is reshaped to form a reshaped first recess. The reshaped first recess has a V-shaped bottom surface. At least a portion of the V-shaped bottom surface comprises one or more steps. A source/drain region is epitaxially grown in the reshaped first recess.
    Type: Application
    Filed: December 21, 2018
    Publication date: May 2, 2019
    Inventors: Chih-Teng Liao, Chih-Shan Chen, Yi-Wei Chiu, Ying Ting Hsia, Tzu-Chan Weng
  • Patent number: 10269917
    Abstract: A method of forming a gate structure includes forming an opening through an insulating layer and forming a first work function metal layer in the opening. The method also includes recessing the first work function metal layer into the opening to form a recessed first work function metal layer, and forming a second work function metal layer in the opening and over the first work function metal layer. The second work function metal layer lines and overhangs the recessed first work function metal layer.
    Type: Grant
    Filed: October 19, 2016
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Chun Chen, Tsung Fan Yin, Li-Te Hsu, Ying Ting Hsia, Yi-Wei Chiu
  • Publication number: 20190088542
    Abstract: A method of forming a semiconductor device includes forming a source/drain region on a substrate and forming a first interlayer dielectric (ILD) layer over the source/drain region. The method further includes forming a first conductive region within the first ILD layer, selectively removing a portion of the first conductive region to form a concave top surface of the first conductive region. The method also includes forming a second ILD layer over the first ILD layer and forming a second conductive region within the second ILD layer and on the concave top surface. The concave top surface provides a large contact area, and hence reduced contact resistance between the first and second conductive regions.
    Type: Application
    Filed: September 24, 2018
    Publication date: March 21, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yun-Yu Hsieh, Jeng Chang Her, Cha-Hsin Chao, Yi-Wei Chiu, Li-Te Hsu, Ying Ting Hsia
  • Publication number: 20190081176
    Abstract: Semiconductor devices, FinFET devices with optimized strained-source-drain recess profiles and methods of forming the same are provided. One of the semiconductor devices includes a substrate, a gate stack over the substrate and a strained layer in a recess of the substrate and aside the gate stack. Besides, a ratio of a depth at the greatest width of the recess to a width of the gate stack ranges from about 0.5 to 0.7.
    Type: Application
    Filed: November 7, 2018
    Publication date: March 14, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ying Ting Hsia, Kun Yu Lin, Ying Ming Wang, Li-Te Hsu