Abstract: Provided is an anti-fuse memory including a anti-fuse memory cell including an isolation structure, a select gate, first and second gate insulating layers, an anti-fuse gate, and first, second and third doped regions. The isolation structure is disposed in a substrate. The select gate is disposed on the substrate. The first gate insulating layer is disposed between the select gate and the substrate. The anti-fuse gate is disposed on the substrate and partially overlapped with the isolation structure. The second gate insulating layer is disposed between the anti-fuse gate and the substrate. The first doped region and the second doped region are disposed in the substrate at opposite sides of the select gate, respectively, wherein the first doped region is located between the select gate and the anti-fuse gate. The third doped region is disposed in the substrate and located between the first doped region and the isolation structure.

Abstract: Provided is an anti-fuse memory including a anti-fuse memory cell including an isolation structure, a select gate, first and second gate insulating layers, an anti-fuse gate, and first, second and third doped regions. The isolation structure is disposed in a substrate. The select gate is disposed on the substrate. The first gate insulating layer is disposed between the select gate and the substrate. The anti-fuse gate is disposed on the substrate and partially overlapped with the isolation structure. The second gate insulating layer is disposed between the anti-fuse gate and the substrate. The first doped region and the second doped region are disposed in the substrate at opposite sides of the select gate, respectively, wherein the first doped region is located between the select gate and the anti-fuse gate. The third doped region is disposed in the substrate and located between the first doped region and the isolation structure.

Abstract: A memory sector with trimmed reference currents, including eight unit cells corresponding to an even word line and eight unit cells corresponding to an odd word line, and each unit cell has erased state and programmed state, wherein the logic state of unit cell corresponding to the odd word line is determined by a first reference current based on cell currents of the 8 unit cells corresponding to the even word line in programmed state and cell currents of the eight unit cells corresponding to the odd word line in erased state, and the logic state of unit cell corresponding to the even word line is determined by a second reference current based on cell currents of the eight unit cells corresponding to the even word line in erased state and cell currents of the 8 unit cells corresponding to the odd word line in programmed state.

Abstract: A memory sector with trimmed reference currents, including eight unit cells corresponding to an even word line and eight unit cells corresponding to an odd word line, and each unit cell has erased state and programmed state, wherein the logic state of unit cell corresponding to the odd word line is determined by a first reference current based on cell currents of the 8 unit cells corresponding to the even word line in programmed state and cell currents of the eight unit cells corresponding to the odd word line in erased state, and the logic state of unit cell corresponding to the even word line is determined by a second reference current based on cell currents of the eight unit cells corresponding to the even word line in erased state and cell currents of the 8 unit cells corresponding to the odd word line in programmed state.

Abstract: A micro light emitting device display apparatus including a circuit substrate, a plurality of micro light emitting devices, a first common electrode layer, and a second common electrode layer is provided. The micro light emitting devices are disposed on the circuit substrate and individually include an epitaxial structure and a first-type electrode and a second-type electrode respectively disposed on two side surfaces of the epitaxial structure opposite to each other. The first common electrode layer is disposed on the circuit substrate and directly covers the plurality of first-type electrodes of the micro light emitting devices. The second common electrode layer is disposed between the micro light emitting devices. The first common electrode layer is electrically connected to the second common electrode layer.

Abstract: A physically unclonable function includes a flash memory, a current comparator and a controller. The flash memory includes a plurality of memory cells. A method of operating the physically unclonable function circuit includes the controller setting the plurality of memory cells to an initial data state, the controller setting the plurality of memory cells between the initial data state and an adjacent data state of the initial data state, the current comparator reading a first current from a memory cell in a first section of the plurality of the memory cells, the current comparator reading a second current from a memory cell in a second section of the plurality of the memory cells, and the current comparator outputting a random bit according to the first current and the second current.

Abstract: A micro component structure includes a substrate, at least one micro component and a fixing structure. The micro component is disposed on the substrate, has a spacing from the substrate and has at least one top surface. The fixing structure is disposed on the substrate and includes at least one covering portion and at least one connecting portion. The covering portion is disposed on a portion of the top surface of the micro component, and the connecting portion is connected to an edge of the covering portion and extends onto the substrate. At least one of the covering portion and the connecting portion includes at least one patterned structure.

Abstract: A micro component structure includes a substrate, at least one micro component and a fixing structure. The micro component is disposed on the substrate, has a spacing from the substrate and has at least one top surface. The fixing structure is disposed on the substrate and includes at least one covering portion and at least one connecting portion. The covering portion is disposed on a portion of the top surface of the micro component, and the connecting portion is connected to an edge of the covering portion and extends onto the substrate. At least one of the covering portion and the connecting portion includes at least one patterned structure.

Abstract: A micro light emitting device display apparatus including a circuit substrate, a plurality of micro light emitting devices, a first common electrode layer, and a second common electrode layer is provided. The micro light emitting devices are disposed on the circuit substrate and individually include an epitaxial structure and a first-type electrode and a second-type electrode respectively disposed on two side surfaces of the epitaxial structure opposite to each other. The first common electrode layer is disposed on the circuit substrate and directly covers the plurality of first-type electrodes of the micro light emitting devices. The second common electrode layer is disposed between the micro light emitting devices. The first common electrode layer is electrically connected to the second common electrode layer.

Abstract: A voltage regulating circuit provides a feedback voltage and an output voltage based on a power voltage. The voltage regulating circuit includes a reference voltage generator and a compensating circuit. The reference voltage generator receives the power voltage, produces the feedback voltage, and includes an impedance having first and second terminals. The second terminal is coupled to a ground voltage and a first current flows through the impedance at the first terminal to produce the feedback voltage. The compensating circuit includes a negative threshold voltage (NVT) transistor having a source terminal, a drain terminal and a gate terminal. The source terminal receives a power voltage, the drain terminal is connected to the gate terminal and coupled to the first terminal of the impedance through a path to add a second current to the first current when the NVT transistor is turned on under an operational condition at the FF corner.

Abstract: A voltage regulating circuit provides a feedback voltage and an output voltage based on a power voltage. The voltage regulating circuit includes a reference voltage generator and a compensating circuit. The reference voltage generator receives the power voltage, produces the feedback voltage, and includes an impedance having first and second terminals. The second terminal is coupled to a ground voltage and a first current flows through the impedance at the first terminal to produce the feedback voltage. The compensating circuit includes a negative threshold voltage (NVT) transistor having a source terminal, a drain terminal and a gate terminal. The source terminal receives a power voltage, the drain terminal is connected to the gate terminal and coupled to the first terminal of the impedance through a path to add a second current to the first current when the NVT transistor is turned on under an operational condition at the FF corner.