Patents by Inventor Ying Trickett

Ying Trickett has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220301930
    Abstract: A method for filling recessed features with a low-resistivity metal. The method includes providing a patterned substrate containing a recessed feature formed in a first layer and a second layer that is exposed in the recessed feature, forming a nucleation enhancement layer on a sidewall of the first layer in the recessed feature and depositing a metal layer in the recessed feature by vapor phase deposition, where the metal layer is deposited on the second layer and on the nucleation enhancement layer. An initial metal layer may be selectively formed on the second layer in the recessed feature before forming the nucleation enhancement layer.
    Type: Application
    Filed: March 7, 2022
    Publication date: September 22, 2022
    Inventors: Kai-Hung Yu, Shihsheng Chang, Ying Trickett, Eric Chih-Fang Liu, Yun Han, Henan Zhang, Cory Wajda, Robert D. Clark, Gerrit J. Leusink, Gyanaranjan Pattanaik, Hiroaki Niimi
  • Patent number: 10861744
    Abstract: A method of processing materials on a semiconductor workpiece using an integrated sequence of processing steps executed on a common manufacturing platform hosting a plurality of processing modules including one or more film-forming modules, one or more etching modules, and one or more transfer modules is provided. A workpiece having an upper planar surface is received into the common manufacturing platform. The method further includes conformally applying a thin film over the feature pattern using one of the film-forming modules, removing the thin film from upper surfaces of the feature pattern using one of the etching modules to leave behind the thin film in the recessed feature, and removing the fill material from the upper planar surface of the workpiece. The integrated sequence of processing steps is executed in a controlled environment within the common manufacturing platform and without leaving the controlled environment.
    Type: Grant
    Filed: March 18, 2019
    Date of Patent: December 8, 2020
    Assignee: Tokyo Electron Limited
    Inventors: Ying Trickett, Kai-Hung Yu, Nicholas Joy, Kaoru Maekawa, Robert Clark
  • Publication number: 20190295887
    Abstract: A method of processing materials on a semiconductor workpiece using an integrated sequence of processing steps executed on a common manufacturing platform hosting a plurality of processing modules including one or more film-forming modules, one or more etching modules, and one or more transfer modules is provided. A workpiece having an upper planar surface is received into the common manufacturing platform. The method further includes conformally applying a thin film over the feature pattern using one of the film-forming modules, removing the thin film from upper surfaces of the feature pattern using one of the etching modules to leave behind the thin film in the recessed feature, and removing the fill material from the upper planar surface of the workpiece. The integrated sequence of processing steps is executed in a controlled environment within the common manufacturing platform and without leaving the controlled environment.
    Type: Application
    Filed: March 18, 2019
    Publication date: September 26, 2019
    Inventors: Ying Trickett, Kai-Hung Yu, Nicholas Joy, Kaoru Maekawa, Robert Clark
  • Patent number: 10008564
    Abstract: Embodiments of the invention describe a method of corner rounding and trimming of nanowires used in semiconductor devices. According to one embodiment, the method includes providing in a process chamber a plurality of nanowires separated from each other by a void, where the plurality of nanowires have a height and at least substantially right angle corners, forming an oxidized surface layer on the plurality of nanowires using an oxidizing microwave plasma, removing the oxidized surface layer to trim the height and round the corners of the plurality of nanowires, and repeating the forming and removing at least once until the plurality of nanowires have a desired trimmed height and rounded corners.
    Type: Grant
    Filed: November 3, 2016
    Date of Patent: June 26, 2018
    Assignee: Tokyo Electron Limited
    Inventors: Kandabara N. Tapily, Ying Trickett, Chihiro Tamura, Cory Wajda, Gerrit J. Leusink, Kaoru Maekawa
  • Publication number: 20170125517
    Abstract: Embodiments of the invention describe a method of corner rounding and trimming of nanowires used in semiconductor devices. According to one embodiment, the method includes providing in a process chamber a plurality of nanowires separated from each other by a void, where the plurality of nanowires have a height and at least substantially right angle corners, forming an oxidized surface layer on the plurality of nanowires using an oxidizing microwave plasma, removing the oxidized surface layer to trim the height and round the corners of the plurality of nanowires, and repeating the forming and removing at least once until the plurality of nanowires have a desired trimmed height and rounded corners.
    Type: Application
    Filed: November 3, 2016
    Publication date: May 4, 2017
    Inventors: Kandabara N. Tapily, Ying Trickett, Chihiro Tamura, Cory Wajda, Gerrit J. Leusink, Kaoru Maekawa