Patents by Inventor Ying-Tsai Chang

Ying-Tsai Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8997034
    Abstract: Techniques for emulation-based functional qualification are disclosed that use an emulation platform to replace simulation in mutation-based analysis. A method for functional qualification of an integrated circuit design includes receiving an integrated circuit design having one or more mutations. Emulation setup and activation simulation are performed in parallel to maximize computing resources. A prototype board can then be programed according to the integrated circuit design and a verification module. A set of test patterns and response generated by a simulation of the integrated circuit using the set of test patterns are stored in a memory of the prototyping board allowing enumeration of mutants to occur at in-circuit emulation speed.
    Type: Grant
    Filed: July 30, 2013
    Date of Patent: March 31, 2015
    Assignee: Synopsys, Inc.
    Inventors: Ying-Tsai Chang, Yu-Chin Hsu
  • Publication number: 20150040096
    Abstract: Techniques for emulation-based functional qualification are disclosed that use an emulation platform to replace simulation in mutation-based analysis. A method for functional qualification of an integrated circuit design includes receiving an integrated circuit design having one or more mutations. Emulation setup and activation simulation are performed in parallel to maximize computing resources. A prototype board can then be programmed according to the integrated circuit design and a verification module. A set of test patterns and response generated by a simulation of the integrated circuit using the set of test patterns are stored in a memory of the prototyping board allowing enumeration of mutants to occur at in-circuit emulation speed.
    Type: Application
    Filed: July 30, 2013
    Publication date: February 5, 2015
    Applicant: Synopsys, Inc.
    Inventors: Ying-Tsai Chang, Yu-Chin Hsu
  • Patent number: 8281280
    Abstract: Methods and systems for testing a design under verification (DUV), the method including receiving, at an interface, configured Field Programmable Gate Array (FPGA) images and runtime control information, wherein each of the FPGA images contains a respective portion of the DUV, and a respective verification module associated with a respective FPGA device. The method further includes, sending, by the interface, each of the FPGA images to each of the respective FPGA devices associated with each of the respective FPGA images. The method also includes, sending, by the interface, timing and control information to each of the respective verification modules based on runtime control information received from the host workstation. In response to receiving timing and control information, each of the respective verification modules, controls each of the respective portions of the DUV in each of the respective FPGA devices.
    Type: Grant
    Filed: February 11, 2011
    Date of Patent: October 2, 2012
    Assignees: SpringSoft, Inc., SpringSoft USA, Inc.
    Inventors: Ying-Tsai Chang, Hwa Mao, Swey-Yan Shei, Ming-Yang Wang, Yu-Chin Hsu
  • Publication number: 20110202894
    Abstract: Methods and systems for testing a prototype, the method including receiving, at a first interface component, a configuration parameter associated with a configured image representative of at least a portion of a user design and an associated verification module. The method further includes, sending, using the first interface component, the configured image to a device. A second interface component may be configured to send timing and control information to the verification module based on at least one of the configuration image and runtime control information received from the first interface component. In response to receiving the timing and control information from the second interface component, the verification module may control the device and/or monitor the device state of at least a portion of the user design.
    Type: Application
    Filed: February 11, 2011
    Publication date: August 18, 2011
    Inventors: Ying-Tsai Chang, Hwa Mao, Swey-Yan Shei, Ming-Yang Wang, Yu-Chin Hsu
  • Patent number: 7571086
    Abstract: A netlist description of a circuit is processed to classify some signals of the circuit as essential signals and to classify all other signals of the circuit as non-essential signals. Thereafter when simulating behavior of the entire circuit in response to input signals supplied over some time interval, a simulator saves first simulation data representing behavior of the circuit's essential signals during the time interval. Thereafter the simulator is programmed to re-simulate behavior of only a selected subcircuit of the circuit during only a selected subinterval of the full time interval based on behavior of essential signals described by the first simulation data. During the re-simulation, the simulator saves second simulation data representing behavior of both essential and non-essential signals of the subcircuit to provide a more complete picture of the behavior of the selected subcircuit during the selected subinterval.
    Type: Grant
    Filed: November 4, 2005
    Date of Patent: August 4, 2009
    Assignee: Springsoft USA, Inc.
    Inventors: Ying-Tsai Chang, Tayung Liu, Yu-Chin Hsu
  • Publication number: 20070106488
    Abstract: A netlist description of a circuit is processed to classify some signals of the circuit as essential signals and to classify all other signals of the circuit as non-essential signals. Thereafter when simulating behavior of the entire circuit in response to input signals supplied over some time interval, a simulator saves first simulation data representing behavior of the circuit's essential signals during the time interval. Thereafter the simulator is programmed to re-simulate behavior of only a selected subcircuit of the circuit during only a selected subinterval of the full time interval based on behavior of essential signals described by the first simulation data. During the re-simulation, the simulator saves second simulation data representing behavior of both essential and non-essential signals of the subcircuit to provide a more complete picture of the behavior of the selected subcircuit during the selected subinterval.
    Type: Application
    Filed: November 4, 2005
    Publication date: May 10, 2007
    Inventors: Ying-Tsai Chang, Tayung Liu, Yu-Chin Hsu