Patents by Inventor Ying Tso

Ying Tso has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11964881
    Abstract: A method for making iridium oxide nanoparticles includes dissolving an iridium salt to obtain a salt-containing solution, mixing a complexing agent with the salt-containing solution to obtain a blend solution, and adding an oxidating agent to the blend solution to obtain a product mixture. A molar ratio of a complexing compound of the complexing agent to the iridium salt is controlled in a predetermined range so as to permit the product mixture to include iridium oxide nanoparticles.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: April 23, 2024
    Assignee: NATIONAL YANG MING CHIAO TUNG UNIVERSITY
    Inventors: Pu-Wei Wu, Yi-Chieh Hsieh, Han-Yi Wang, Kuang-Chih Tso, Tzu-Ying Chan, Chung-Kai Chang, Chi-Shih Chen, Yu-Ting Cheng
  • Patent number: 11914269
    Abstract: A laser processing system includes a laser source, an optical splitting unit, a frequency conversion unit and at least one optical mixer. The optical splitting unit is provided to divide light emitted by the laser source into a first light and a second light, and the first light and the second light have the same wavelength range. The frequency conversion unit is provided to convert the second light into a working light. The working light includes a frequency converted light, and the frequency converted light and the second light have different wavelength ranges. The optical mixer is provided to mix the first light with the frequency converted light.
    Type: Grant
    Filed: November 10, 2020
    Date of Patent: February 27, 2024
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Zih-Yi Li, Ying-Tso Lin, Shang-Yu Hsu, Ying-Hui Yang
  • Patent number: 11547021
    Abstract: An immersion cooling system includes a receiving member, a heat dissipation channel, and a heat sink. The receiving member is filled with coolant. The receiving member is connected to an end of the heat sink, and heat-generating entities such as one or more servers are positioned in a cavity of the receiving member. The heat dissipation channel is connected to the cavity and is connected to the heat sink. The heat dissipation channel communicates with the cavity and allows circulation of the coolant in the channel, the heat sink cooling down the coolant flowing into heat dissipation channel from the cavity. The immersion cooling system is compact, occupies very little space, and is easily installed, maintained, and moved. A server system having the immersion cooling system is also disclosed.
    Type: Grant
    Filed: April 29, 2021
    Date of Patent: January 3, 2023
    Assignee: Fulian Precision Electronics (Tianjin) Co., LTD.
    Inventors: Wei-Hsiang Hsiao, Ying-Tso Lai
  • Publication number: 20220151111
    Abstract: An immersion cooling system includes a receiving member, a heat dissipation channel, and a heat sink. The receiving member is filled with coolant. The receiving member is connected to an end of the heat sink, and heat-generating entities such as one or more servers are positioned in a cavity of the receiving member. The heat dissipation channel is connected to the cavity and is connected to the heat sink. The heat dissipation channel communicates with the cavity and allows circulation of the coolant in the channel, the heat sink cooling down the coolant flowing into heat dissipation channel from the cavity. The immersion cooling system is compact, occupies very little space, and is easily installed, maintained, and moved. A server system having the immersion cooling system is also disclosed.
    Type: Application
    Filed: April 29, 2021
    Publication date: May 12, 2022
    Inventors: WEI-HSIANG HSIAO, YING-TSO LAI
  • Publication number: 20220082900
    Abstract: A laser processing system includes a laser source, an optical splitting unit, a frequency conversion unit and at least one optical mixer. The optical splitting unit is provided to divide light emitted by the laser source into a first light and a second light, and the first light and the second light have the same wavelength range. The frequency conversion unit is provided to convert the second light into a working light. The working light includes a frequency converted light, and the frequency converted light and the second light have different wavelength ranges. The optical mixer is provided to mix the first light with the frequency converted light.
    Type: Application
    Filed: November 10, 2020
    Publication date: March 17, 2022
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Zih-Yi LI, Ying-Tso LIN, Shang-Yu HSU, Ying-Hui YANG
  • Publication number: 20180117710
    Abstract: Disclosed is a laser system and a laser flare machining method. The laser system includes a laser light source, a splitter element, and a scanning lens assembly. The laser light source projects a first light beam. The splitter element is furnished on a first path along which the first light beam travels, and splits the first light beam into a second light beam traveling along a second path and a third light beam traveling along a third path. The scanning lens assembly is furnished on the second path and the third path, and focus the second light beam and the third light beam at a machining position to process a work piece.
    Type: Application
    Filed: December 22, 2016
    Publication date: May 3, 2018
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Shih-Ting LIN, Ying-Tso LIN, Hong-Xi TSAU
  • Patent number: 9554839
    Abstract: An injection device includes a housing, a plunger, and a heating unit. The plunger is slidably arranged within the housing thereby performing a plunging movement therein. The heating unit is disposed within the housing for generating a heat energy inside the housing such that a filling material inside the housing can be soften and be transformed into a movable filling material with viscosity by absorbing the heat energy from the heating unit.
    Type: Grant
    Filed: July 18, 2013
    Date of Patent: January 31, 2017
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Ying-Tso Lin, Chi-Feng Chan, Chieh Hu, Chun-Jen Liao
  • Patent number: 9312139
    Abstract: A semiconductor element and a manufacturing method of the same are provided. The semiconductor element includes a substrate, a plurality of doping strips, a memory material layer, a plurality of conductive damascene structures, and a dielectric structure. The doping strips are formed in the substrate. The memory material layer is formed on the substrate, and the memory material layer comprises a memory area located on two sides of the doping strips. The conductive damascene structures are formed on the memory material layer. The dielectric structure is formed on the doping strips and between the conductive damascene structures. The conductive damascene structures are extended in a direction perpendicular to a direction which the doping strips are extended in.
    Type: Grant
    Filed: May 10, 2013
    Date of Patent: April 12, 2016
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Ching-Hung Wang, Jyun-Siang Huang, Chien-Hung Liu, Chia-Wen Cheng, Ying-Tso Chen
  • Publication number: 20160079950
    Abstract: A printed circuit board (PCB) includes a top outer layer, a bottom outer layer, a signal transmission layer, an inner signal transmission layer, and a via system defined in the PCB. The via system includes two pairs of vias configured to transmit signals from a transmitter to a receiver. A signal transmission pathway is defined in the top outer layer, the signal transmission layer, and the inner signal transmission layer. Signals are sent from the transmitter to a first pair of vias, the signals are transmitted from the first pair of vias to a second pair of vias, and the signals are sent from the second pair of vias to the receiver. The two pairs of vias and the signal transmission pathway provide impedance matching to the signals.
    Type: Application
    Filed: September 12, 2014
    Publication date: March 17, 2016
    Inventors: MING-HSIEN CHENG, PO-CHUAN HSIEH, YING-TSO LAI, CHIEN-HSUN CHEN
  • Patent number: 9276549
    Abstract: A printed circuit board (PCB) includes a top outer layer, a bottom outer layer, a signal transmission layer, an inner signal transmission layer, and a via system defined in the PCB. The via system includes two pairs of vias configured to transmit signals from a transmitter to a receiver. A signal transmission pathway is defined in the top outer layer, the signal transmission layer, and the inner signal transmission layer. Signals are sent from the transmitter to a first pair of vias, the signals are transmitted from the first pair of vias to a second pair of vias, and the signals are sent from the second pair of vias to the receiver. The two pairs of vias and the signal transmission pathway provide impedance matching to the signals.
    Type: Grant
    Filed: September 12, 2014
    Date of Patent: March 1, 2016
    Assignee: ScienBiziP Consulting(Shenzhen)Co., Ltd.
    Inventors: Ming-Hsien Cheng, Po-Chuan Hsieh, Ying-Tso Lai, Chien-Hsun Chen
  • Patent number: 9101074
    Abstract: A capacitor includes a first patterned conductive layer, a second patterned conductive layer and a first patterned dielectric layer. The first patterned conductive layer resembles a comb with internal teeth, and the second patterned conductive layer resembles a comb with external teeth, the internal and the external teeth being interlaced in one plane. A thin first patterned dielectric layer within the same plane is shaped and arranged to infill all the gaps between the teeth. The first patterned conductive layer, the second patterned conductive layer, and the first patterned dielectric layer create a single coplanar layer, and a number of such interconnected coplanar layers are stacked within and contained by a multilayer circuit board.
    Type: Grant
    Filed: June 27, 2013
    Date of Patent: August 4, 2015
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Ying-Tso Lai, Hsiao-Yun Su
  • Patent number: 8969202
    Abstract: A method of manufacturing a metal silicide is disclosed below. A substrate having a first region and a second region is provided. A silicon layer is formed on the substrate. A planarization process is performed to make the silicon layer having a planar surface. A part of the silicon layer is removed to form a plurality of first gates on the first region and to form a plurality of second gates on the second region. The height of the first gates is greater than the height of the second gates, and top surfaces of the first gates and the second gates have the same height level. A dielectric layer covering the first gates and the second gates is formed and exposes the top surfaces of the first gates and the second gates. A metal silicide is formed on the top surfaces of the first gates and the second gates.
    Type: Grant
    Filed: February 7, 2014
    Date of Patent: March 3, 2015
    Assignee: Macronix International Co., Ltd.
    Inventors: Yen-Hao Shih, Ying-Tso Chen, Shih-Chang Tsai, Chun-Fu Chen
  • Patent number: 8953301
    Abstract: A capacitor includes at least two electrode layers opposite to each other and a dielectric layer positioned between the at least two electrode layers. The at least two electrode layers have opposite polarities. Each electrode layer includes a positive electrode and a negative electrode. The positive electrode includes a plurality of first coupling portions spaced substantially evenly and arranged in parallel. The negative electrode includes a plurality of second coupling portions spaced substantially evenly and arranged in parallel. The positive electrode and the negative electrode of each electrode layer are coplanar, and the plurality of first coupling portions interlace with the plurality of second coupling portions.
    Type: Grant
    Filed: September 26, 2012
    Date of Patent: February 10, 2015
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventors: Ying-Tso Lai, Hsiao-Yun Su
  • Patent number: 8898854
    Abstract: An plug storage structure of a cleaning robot is presented. A charging structure includes a charging base and a main body of an electronic device. The charging base includes a charging terminal and a projecting portion. The main body has an external housing, charging plugs and an plug storage device. When the main body reaches the charging base, the projecting portion triggers the plug storage device, so that the charging plugs protrude from the external housing, so as to be connected to the charging terminal. When the main body leaves the charging base, the plug storage device automatically receives the charging plugs inside the external housing, so as to keep the plugs of the cleaning robot received inside the external housing during cleaning, thereby preventing the plugs of the cleaning robot from colliding with and damaging adjacent furniture.
    Type: Grant
    Filed: August 5, 2011
    Date of Patent: December 2, 2014
    Assignee: MSI Computer (Shenzhen) Co., Ltd.
    Inventors: Tse-Ying Tso, You-Wei Teng
  • Publication number: 20140303920
    Abstract: A system and a method for ESD testing are contained in an ESD testing system which is running on an electronic device. A storage unit of the electronic device pre-stores a layout file which includes a layout pattern having electrical traces, an ESD entry point, and mounted positions of multiple electronic elements. The ESD testing method obtains the layout file from the storage unit; displays the layout pattern on a display unit of the electronic device, simulates ESD in the ESD entry point of the displayed layout pattern, tests electrical characteristics of the electrical traces between the ESD entry point and the mounted positions of multiple electronic elements to determine whether the electrical characteristics of the electrical traces pass or fail the ESD test, and marks the electrical traces which fail the ESD test on the displayed layout pattern.
    Type: Application
    Filed: March 31, 2014
    Publication date: October 9, 2014
    Applicant: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: WEI-CHIEH CHOU, YING-TSO LAI, EN-SHUO CHANG, CHUN-JEN CHEN
  • Publication number: 20140264545
    Abstract: A semiconductor element and a manufacturing method of the same are provided. The semiconductor element includes a substrate, a plurality of doping strips, a memory material layer, a plurality of conductive damascene structures, and a dielectric structure. The doping strips are formed in the substrate. The memory material layer is formed on the substrate, and the memory material layer comprises a memory area located on two sides of the doping strips. The conductive damascene structures are formed on the memory material layer. The dielectric structure is formed on the doping strips and between the conductive damascene structures. The conductive damascene structures are extended in a direction perpendicular to a direction which the doping strips are extended in.
    Type: Application
    Filed: May 10, 2013
    Publication date: September 18, 2014
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Ching-Hung Wang, Jyun-Siang Huang, Chien-Hung Liu, Chia-Wen Cheng, Ying-Tso Chen
  • Patent number: 8809933
    Abstract: A semiconductor device including a substrate, a plurality of stacked gate structures, a plurality of doped regions, a plurality of liner layers, a plurality of conductive layers, a plurality of dielectric layers and a plurality of word lines is provided. The substrate has a plurality of trenches therein. The stacked gate structures are on the substrate between the trenches. The doped regions are in the substrate at sidewalls or bottoms of the trenches. The liner layers are on at least a portion of sidewalls of the stacked gate structures and on sidewalls of the trenches. The conductive layers are in the trenches and electrically connected to the doped regions. The dielectric layers are on the conductive layers and between the stacked gate structures. The word lines are on the substrate and electrically connected to the stacked gate structures.
    Type: Grant
    Filed: July 12, 2010
    Date of Patent: August 19, 2014
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Guan-De Lee, Chien-Hung Liu, Shou-Wei Huang, Ying-Tso Chen
  • Patent number: 8793631
    Abstract: In a computing device, a computerized method and a non-transitory storage medium are applied in checking whether the transmission lines in a stored wiring diagram meet a certain criterion in relation to vias in the routes of differential pairs. A transmission line is selected to determine whether or not the line belongs to a differential pair and passes through at least one via. Another transmission line of the differential pair is obtained for analysis when the selected transmission line passes through at least one via. Sizes of vias in the respective routes of the differential pair are compared and a distance between the vias of the differential pair is compared. The differential pair, and the sizes of vias which comply or do not comply with the criterion are recorded and displayed in a list of results.
    Type: Grant
    Filed: June 27, 2013
    Date of Patent: July 29, 2014
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventors: Dan-Chen Wu, Chun-Jen Chen, Ying Tso
  • Patent number: 8766740
    Abstract: An equalizer for compensating transmission losses of electronic communication signals includes a circuit board and a compensation module. The compensation module includes a pair of input pins, a pair of output pins, and at least two resistors. When a signal transmitted by the circuit board is received by the input pins, a first portion of the signal is directly output from the output pins, a second portion of the signal is reflected by the first resistor and transmitted back to the output pins to output, and a third portion of the signal is reflected by the second resistor and transmitted back to the output pins to output, such that output of the equalizer applies two stages of compensation.
    Type: Grant
    Filed: November 27, 2012
    Date of Patent: July 1, 2014
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventors: Po-Chuan Hsieh, Ying-Tso Lai, Cheng-Hsien Lee, En-Shuo Chang
  • Publication number: 20140163567
    Abstract: An injection device includes a housing, a plunger, and a heating unit. The plunger is slidably arranged within the housing thereby performing a plunging movement therein. The heating unit is disposed within the housing for generating a heat energy inside the housing such that a filling material inside the housing can be soften and be transformed into a movable filling material with viscosity by absorbing the heat energy from the heating unit.
    Type: Application
    Filed: July 18, 2013
    Publication date: June 12, 2014
    Inventors: YING-TSO LIN, CHI-FENG CHAN, CHIEH HU, CHUN-JEN LIAO