Patents by Inventor Ying-Tsung Chu
Ying-Tsung Chu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11837564Abstract: The invention provides a semiconductor bonding structure, the semiconductor bonding structure includes a first chip and a second chip which are bonded with each other, the first chip has a first bonding pad and the second bonding pad contacted and electrically connected to each other on a bonding interface, the first bonding pad and the second bonding pad are made of copper, and a heterogeneous contact combination in the first chip, the heterogeneous contact combination comprises a contact stack structure of a copper element, a tungsten element and an aluminum element, the tungsten element is located between the copper element and the aluminum element.Type: GrantFiled: August 10, 2021Date of Patent: December 5, 2023Assignee: Powerchip Semiconductor Manufacturing CorporationInventors: Chun-Lin Lu, Shou-Zen Chang, Ying-Tsung Chu, Chi-Ming Chen
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Publication number: 20230034412Abstract: A wafer structure and a manufacturing method thereof are provided. The wafer structure includes a substrate structure, a first dielectric layer, multiple test pads, a second dielectric layer, and multiple bond pads. The first dielectric layer is disposed on the substrate structure. The test pads are disposed in and exposed outside the first dielectric layer. Each test pad has a probe mark. The second dielectric layer is disposed on the first dielectric layer. The second dielectric layer has a top surface away from the test pads. Multiple bond pads are disposed in and exposed outside the second dielectric layer. Each bond pad is electrically connected to the corresponding test pad. The bond pads have bonding surfaces away from the test pads. The bonding surfaces are flush with the top surface. In the normal direction of the substrate structure, each bond pad does not overlap the probe mark of the corresponding test pad.Type: ApplicationFiled: March 31, 2022Publication date: February 2, 2023Applicant: Powerchip Semiconductor Manufacturing CorporationInventors: Chun-Lin Lu, Shou-Zen Chang, Ying-Tsung Chu, Ming-Hsun Tsai
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Publication number: 20230018214Abstract: The invention provides a semiconductor bonding structure, the semiconductor bonding structure includes a first chip and a second chip which are bonded with each other, the first chip has a first bonding pad and the second bonding pad contacted and electrically connected to each other on a bonding interface, the first bonding pad and the second bonding pad are made of copper, and a heterogeneous contact combination in the first chip, the heterogeneous contact combination comprises a contact stack structure of a copper element, a tungsten element and an aluminum element, the tungsten element is located between the copper element and the aluminum elementType: ApplicationFiled: August 10, 2021Publication date: January 19, 2023Applicant: Powerchip Semiconductor Manufacturing CorporationInventors: Chun-Lin Lu, Shou-Zen Chang, Ying-Tsung Chu, Chi-Ming Chen
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Patent number: 11335691Abstract: A memory structure including a substrate, a memory cell, and a transistor is provided. The substrate includes a memory cell region and a peripheral circuit region. The memory cell is located in the memory cell region. The transistor is located in the peripheral circuit region. The transistor includes a gate, a first doped region, a second doped region, a first nickel silicide layer, and a second nickel silicide layer. The gate is located on the substrate and is insulated from the substrate. The first doped region and the second doped region are located in the substrate on two sides of the gate. The first nickel silicide layer is located on an entire top surface of the first doped region, and the second nickel silicide layer is located on an entire top surface of the second doped region.Type: GrantFiled: February 22, 2021Date of Patent: May 17, 2022Assignee: Powerchip Semiconductor Manufacturing CorporationInventors: Ying-Tsung Chu, Ching-Kang Chiu, Ching-Sung Ho
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Publication number: 20210175237Abstract: A memory structure including a substrate, a memory cell, and a transistor is provided. The substrate includes a memory cell region and a peripheral circuit region. The memory cell is located in the memory cell region. The transistor is located in the peripheral circuit region. The transistor includes a gate, a first doped region, a second doped region, a first nickel silicide layer, and a second nickel silicide layer. The gate is located on the substrate and is insulated from the substrate. The first doped region and the second doped region are located in the substrate on two sides of the gate. The first nickel silicide layer is located on an entire top surface of the first doped region, and the second nickel silicide layer is located on an entire top surface of the second doped region.Type: ApplicationFiled: February 22, 2021Publication date: June 10, 2021Applicant: Powerchip Semiconductor Manufacturing CorporationInventors: Ying-Tsung Chu, Ching-Kang Chiu, Ching-Sung Ho
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Patent number: 10971501Abstract: A memory structure including a substrate, a memory cell, and a transistor is provided. The substrate includes a memory cell region and a peripheral circuit region. The memory cell is located in the memory cell region. The transistor is located in the peripheral circuit region. The transistor includes a gate, a first doped region, a second doped region, a first nickel silicide layer, and a second nickel silicide layer. The gate is located on the substrate and is insulated from the substrate. The first doped region and the second doped region are located in the substrate on two sides of the gate. The first nickel silicide layer is located on an entire top surface of the first doped region, and the second nickel silicide layer is located on an entire top surface of the second doped region.Type: GrantFiled: May 29, 2019Date of Patent: April 6, 2021Assignee: Powerchip Semiconductor Manufacturing CorporationInventors: Ying-Tsung Chu, Ching-Kang Chiu, Ching-Sung Ho
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Publication number: 20200328215Abstract: A memory structure including a substrate, a memory cell, and a transistor is provided. The substrate includes a memory cell region and a peripheral circuit region. The memory cell is located in the memory cell region. The transistor is located in the peripheral circuit region. The transistor includes a gate, a first doped region, a second doped region, a first nickel silicide layer, and a second nickel silicide layer. The gate is located on the substrate and is insulated from the substrate. The first doped region and the second doped region are located in the substrate on two sides of the gate. The first nickel silicide layer is located on an entire top surface of the first doped region, and the second nickel silicide layer is located on an entire top surface of the second doped region.Type: ApplicationFiled: May 29, 2019Publication date: October 15, 2020Applicant: Powerchip Semiconductor Manufacturing CorporationInventors: Ying-Tsung Chu, Ching-Kang Chiu, Ching-Sung Ho