Patents by Inventor Ying-Tsung WU

Ying-Tsung WU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • IGBT device with narrow mesa and manufacture thereof
    Patent number: 11677019
    Abstract: The present application provides an insulated gate bipolar transistor (IGBT) device with narrow mesa and a manufacture thereof. The device comprises: a semiconductor substrate; gate trench structures and emitter trench structures formed on front surface of the semiconductor substrate and alternately arranged along with horizontal direction; wherein the gate trench structures and the emitter trench structures are respectively set in pair along with the arrangement direction, and the pairs of the gate trench structures and the pairs of the emitter trench structures are set in alternate arrangement along with the arrangement direction; well regions formed between the emitter trench structures of one pair; emitter injection regions formed between the gate trench structures of one pair and between the emitter trench structures of one pair, respectively; and wherein, in the region between the emitter trench structures of the one pair, the emitter injection region is above the well region.
    Type: Grant
    Filed: June 15, 2021
    Date of Patent: June 13, 2023
    Assignee: SiEn (QingDao) Integrated Circuits Co., Ltd.
    Inventors: Min-Hwa Chi, Ching-Ju Lin, Ying-Tsung Wu, Conghui Liu, Longkang Yang, Huan Wang, Richard Ru-Gin Chang
  • IGBT DEVICE WITH NARROW MESA AND MANUFACTURE THEREOF
    Publication number: 20210391453
    Abstract: The present application provides an insulated gate bipolar transistor (IGBT) device with narrow mesa and a manufacture thereof. The device comprises: a semiconductor substrate; gate trench structures and emitter trench structures formed on front surface of the semiconductor substrate and alternately arranged along with horizontal direction; wherein the gate trench structures and the emitter trench structures are respectively set in pair along with the arrangement direction, and the pairs of the gate trench structures and the pairs of the emitter trench structures are set in alternate arrangement along with the arrangement direction; well regions formed between the emitter trench structures of one pair; emitter injection regions formed between the gate trench structures of one pair and between the emitter trench structures of one pair, respectively; and wherein, in the region between the emitter trench structures of the one pair, the emitter injection region is above the well region.
    Type: Application
    Filed: June 15, 2021
    Publication date: December 16, 2021
    Applicant: SiEn (QingDao) Integrated Circuits Co., Ltd.
    Inventors: Min-Hwa CHI, Ching-Ju LIN, Ying-Tsung WU, Conghui LIU, Longkang YANG, Huan WANG, Richard Ru-Gin CHANG