Patents by Inventor Ying-Tu Chen

Ying-Tu Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9082660
    Abstract: A method of controlling a threshold voltage is provided. The method of controlling a threshold voltage includes performing a film-thickness measuring step to measure the thickness of a film layer on a wafer to obtain a film-thickness value. Then, at least one parameter is decided, selected, or generated according to the film-thickness value. Next, an ion implantation process is performed on the wafer, wherein the ion implantation process is executed according to the parameter to form a threshold voltage adjustment region in the wafer below the film layer.
    Type: Grant
    Filed: August 13, 2013
    Date of Patent: July 14, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Ji Feng, Hai-Long Gu, Ying-Tu Chen
  • Publication number: 20150140778
    Abstract: A method for manufacturing the MIM capacitor structure is provided. A first damascene electrode layer is formed in the first opening formed in a first dielectric layer. An insulating barrier layer is formed to cover the first dielectric layer and the first damascene electrode layer. A second opening and a third opening are formed in the second dielectric layer formed on the insulating barrier layer. The second opening and the third opening are located above the first damascene electrode layer to expose a portion of the insulating barrier layer therefrom. The insulating barrier layer in the third opening is removed to expose a portion of the first damascene electrode layer. A second damascene electrode layer is formed in the second opening to be contacted with the insulating barrier layer and a dual damascene structure is formed in the third opening to be contacted with the first damascene electrode layer.
    Type: Application
    Filed: December 22, 2014
    Publication date: May 21, 2015
    Applicant: UNITED MICROELECTRONICS CORPORATION
    Inventors: JI FENG, DUAN-QUAN LIAO, HAI-LONG GU, YING-TU CHEN
  • Publication number: 20150050751
    Abstract: A method of controlling a threshold voltage is provided. The method of controlling a threshold voltage includes performing a film-thickness measuring step to measure the thickness of a film layer on a wafer to obtain a film-thickness value. Then, at least one parameter is decided, selected, or generated according to the film-thickness value. Next, an ion implantation process is performed on the wafer, wherein the ion implantation process is executed according to the parameter to form a threshold voltage adjustment region in the wafer below the film layer.
    Type: Application
    Filed: August 13, 2013
    Publication date: February 19, 2015
    Applicant: United Microelectronics Corp.
    Inventors: Ji Feng, Hai-Long Gu, Ying-Tu Chen
  • Patent number: 8946854
    Abstract: A metal-insulator-metal (MIM) capacitor structure includes a first dielectric layer, a first damascene electrode layer, an insulating barrier layer, a second dielectric layer and a second damascene electrode layer. The first damascene electrode layer is formed in the first dielectric layer. The insulating barrier layer covers the first dielectric layer and the first damascene electrode layer, and is a single layer structure. The second dielectric layer is formed on the insulating barrier layer. The second damascene electrode layer is formed in the second dielectric layer and is contacted with the insulating barrier layer. The MIM capacitor structure can includes a dual damascene structure formed in the second dielectric layer and the insulating barrier layer and electrically connected to the first damascene electrode layer. A method for manufacturing the MIM capacitor structure is also provided.
    Type: Grant
    Filed: November 9, 2011
    Date of Patent: February 3, 2015
    Assignee: United Microelectronics Corporation
    Inventors: Ji Feng, Duan-Quan Liao, Hai-Long Gu, Ying-Tu Chen
  • Publication number: 20140357050
    Abstract: A method of forming an isolation structure and a through silicon via includes the following steps. First, at least a first trench and at least a second trench are formed in the substrate by a single etch step. Then, an insulating layer is formed to simultaneously fill up the first trench and cover a sidewall and a bottom of the second trench. After that, a conductive layer is formed to fill in the second trench. Subsequently, the insulating layer and the conductive layer on a front side of the substrate are removed. Later, a back side of the substrate is thinned to expose the conductive layer in the second trench. The insulating layer in the first trench serves as an insulating filling, and the insulating layer on the sidewall of the second trench serves as a liner of the through silicon via.
    Type: Application
    Filed: June 3, 2013
    Publication date: December 4, 2014
    Inventors: JI FENG, XIAOQING XU, Hailong Gu, Ying-Tu Chen, JINGLING WANG
  • Publication number: 20130200519
    Abstract: The present invention relates to a method of fabricating a through silicon via (TSV) structure, in which, a dielectric layer is disposed to cover surface of each of a device region of a substrate and a sidewall and a bottom of a via hole in a TSV region of the substrate, and the via hole having the dielectric layer covering the sidewall and the bottom is filled with a conductive material. The present invention also relates to a TSV structure, in which, a dielectric layer disposed in the device region of a substrate extends to the via hole in a TSV region of the substrate to cover surface of the sidewall of the via hole to serve as a dielectric liner, and a conductive material is filled into the via hole having the dielectric layer covering the sidewall.
    Type: Application
    Filed: February 2, 2012
    Publication date: August 8, 2013
    Inventors: Ji Feng, Hailong Gu, Ying-Tu Chen, Jing-Ling Wang
  • Publication number: 20130113075
    Abstract: A metal-insulator-metal (MIM) capacitor structure includes a first dielectric layer, a first damascene electrode layer, an insulating barrier layer, a second dielectric layer and a second damascene electrode layer. The first damascene electrode layer is formed in the first dielectric layer. The insulating barrier layer covers the first dielectric layer and the first damascene electrode layer, and is a single layer structure. The second dielectric layer is formed on the insulating barrier layer. The second damascene electrode layer is formed in the second dielectric layer and is contacted with the insulating barrier layer. The MIM capacitor structure can includes a dual damascene structure formed in the second dielectric layer and the insulating barrier layer and electrically connected to the first damascene electrode layer. A method for manufacturing the MIM capacitor structure is also provided.
    Type: Application
    Filed: November 9, 2011
    Publication date: May 9, 2013
    Applicant: UNITED MICROELECTRONICS CORPORATION
    Inventors: Ji FENG, Duan-Quan Liao, Hai-Long Gu, Ying-Tu Chen