Abstract: The present invention provides a method utilizing the fabrication process of poly-Si spacers to build a flash memory with 2bit/cell. In the present invention, recessed poly-Si spacers are used to fabricate discontinuous floating gates below a control gate to build a flash memory with 2bit/cell. The present invention is characterized in that the fabrication process of poly-Si spacers is exploited to complete the fabrication process of floating gates in automatic alignment way without any extra mask process. Moreover, each memory cell in this flash memory can store two bits, hence increasing the memory capacity.

Abstract: The present invention provides a method utilizing the fabrication process of poly-Si spacers to build a flash memory with 2 bit/cell. In the present invention, recessed poly-Si spacers are used to fabricate discontinuous floating gates below a control gate to build a flash memory with 2 bit/cell. The present invention is characterized in that the fabrication process of poly-Si spacers is exploited to complete the fabrication process of floating gates in automatic alignment way without any extra mask process. Moreover, each memory cell in this flash memory can store two bits, hence increasing the memory capacity.

Abstract: The present invention generally relates to provide a dual-bit metal oxide nitride oxide semiconductor (MONOS)/semiconductor oxide nitride oxide semiconductor (SONOS) memory structure which is provided with a non-continuous floating gate. In a single memory device, the present invention utilizes a non-continuous floating gate for using as the dual-point electric charge storing unit. However, these two electric charge storing points are controlled by the source and the drain of the device. Utilizing a memory storing two bits can increase the memory content. Furthermore, electric charges stored in these two bits do not cross talk to each other so as the present invention can improve and enhance the reliability of the memory device.

Abstract: The present invention discloses a method of utilizing the fabrication process of floating gate spacer to build a twin-bit MONOS/SONOS memory, wherein recessed ONO spacers are used to fabricate a discontinuous floating gate below a poly control gate to obtain a MONOS/SONOS memory device having twinbit memory cells. Cross talk between charges stored in the two bits can be avoided, hence enhancing the reliability of memory device. Moreover, if the voltage Vt varies during the fabrication process, the device can restore its normal characteristics through the individual and separate characteristic of the two bits and by using program or erase condition. The present invention can utilize the fabrication process of ONO spacer to complete the fabrication process of floating gate in automatic alignment way without the need of undergoing several mask processes.

Abstract: A dual-bit flash memory forming by discontinuous floating gates is disclosed. The memory cell of the dual-bit flash memory contains a P type semiconductor substrate or an N type semiconductor substrate with a source and a drain therein. At least two floating gates are installed on the semiconductor substrate between the source and the drain. A tunneling dielectric layer is used to isolate the floating gates and the semiconductor substrate. An insulated dielectric layer is formed on the surface of the floating gates and the central exposed semiconductor substrate. Then, another control gate is formed on the insulated dielectric layer. Thereby, a dual-bit flash memory cell is formed. In the present invention, under a condition of without increasing the density of the unit memory cell, the capacity of memory is twice.