Abstract: A method for generating header and groove/land transition flags using the DPD technology and an apparatus using the same are disclosed. The method first sets a first and a second threshold levels. Then, the method generates a phase difference signal. The method generates a first transition flag signal and a second transition flag signal, wherein the first transition flag signal is enabled when the phase difference signal is greater than the first threshold level and the second transition flag signal is enabled when the phase difference signal is smaller than the second threshold level. The method then generates a header flag signal according to the first and the second transition flag signal.

Abstract: A method for generating header and transition flags using the DPD technology and an optical device using the same are disclosed. The method first sets a first and a second threshold levels. Then, the method generates a phase difference signal, i.e. starting a phase detection function to generate a phase difference signal. The method generates a first transition flag signal and a second transition flag signal, wherein the first transition flag signal is enable if the phase difference signal is greater than a first threshold level and the second transition flag signal is enable if the phase difference signal is smaller than the second threshold level. The method then generates a first header flag signal and a second header flag signal according to the transition flag signal.

Abstract: A method for generating header and transition flags using the DPD technology and an optical device using the same are disclosed. The method first sets a first and a second threshold levels. Then, the method generates a phase difference signal, i.e. starting a phase detection function to generate a phase difference signal. The method generates a first transition flag signal and a second transition flag signal, wherein the first transition flag signal is enable if the phase difference signal is greater than a first threshold level and the second transition flag signal is enable if the phase difference signal is smaller than the second threshold level. The method then generates a first header flag signal and a second header flag signal according to the transition flag signal.

Abstract: A current cell for converting a digital signal to an analog current signal is disclosed. The current cell includes a first PMOS transistor which receives the digital signal from a pre-stage processor by the gate. A drain of the first PMOS transistor is grounded. A second PMOS transistor has a source which is connected to the source of the first PMOS transistor, a gate which receives an inverse signal of the digital signal from the pre-stage processor, and a drain for providing the analog current signal. A third PMOS transistor is connected between a voltage source and the source of the first PMOS transistor. The third PMOS transistor has a gate to which a first reference voltage is applied.

Abstract: A differential-type voltage-controlled oscillator (VCO) with low-frequency stability compensation is disclosed. The differential-type VCO comprises a voltage-to-current converter for converting an input voltage signal into a biasing current signal to control the frequency of the VCO output. The VCO further comprises a number of stages of differential amplifiers connected in cascade. Each of the stages of differential amplifiers includes a pair of differential input PMOS transistors, with each of the PMOS transistors connected to a pair of NMOS load transistors. Each of the pair of NMOS load transistors are connected in parallel. The VCO further comprises a number of stages of bias circuits connected in cascade. Each of the bias circuits is connected to a corresponding stage of the differential amplifiers for receiving the bias current generated by the voltage-to-current converter.

Abstract: A lateral bipolar transistor and method of making the transistor are disclosed. The device is made by etching a trench around a central region of a semiconductor body. An emitter is buried beneath the surface of this central area and contact to it is made via a self-alignment technique. The collector region of the transistor is contacted through the floor of the trench while the base region of the transistor is contacted in a region that surrounds the trench. The described method is compatible with the simultaneous manufacture of FET devices on the same chip.

Abstract: A process of fabricating a bipolar junction transistor forms, on the substrate, a masking layer including an opening, an intermediate masking portion surrounded by the opening and an outer masking portion. The masking layer consists of a pad oxide and a silicon nitride. A photoresist is then formed on the outer masking portion. A first ion implantation process at a relatively low dose and a relatively high energy is performed to form a base region underlying the intermediate masking portion, and a second ion implantation process at a relatively high dose and a relatively low energy is performed to form a base contact region underlying the opening. Then, the photoresist is removed. A field oxide is grown in the opening of the masking layer, followed by removing the masking layer.

Abstract: A lateral bipolar transistor and method of making the transistor are disclosed. The device is made by etching a trench around a central region of a semiconductor body. An emitter is buried beneath the surface of this central area and contact to it is made via a self-alignment technique. The collector region of the transistor is contacted through the floor of the trench while the base region of the transistor is contacted in a region that surrounds the trench. The described method is compatible with the simultaneous manufacture of FET devices on the same chip.