Abstract: Parity for the address of a low order zero in an input data word is generated directly from the input data rather than from the address of the low order zero. A find low order zero circuit (11) generates an address of the low order zero in the data word. Simultaneously with this operation a parity generating circuit (12) operates on the input data word to generate parity for the low order zero address. The parity generating circuit comprises a plurality of individual circuits (30 through 33) each of which operates on a different byte of the input data word. The individual circuits each generate a control signal (E.sub.a,E.sub.b . . . ) according to whether or not its byte contains a low order order zero, and a result signal (R.sub.a,R.sub.b . . . ) which represents the parity of the address of the low order zero, if any, in the byte taking into account the byte position in the input data word. Logic circuitry combines the control and result signals to form the overall parity for the low order zero address.