Patents by Inventor Ying-Wei Tseng

Ying-Wei Tseng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240211787
    Abstract: An electronic device and method for performing Monte Carlo analysis based on a quantum circuit are provided. The method includes: exciting, by quantum gates, a plurality of qubits into a plurality of states; selecting, by a probability measurement circuit, a sampled result randomly from a plurality of operation results of a quantum circuit when measuring the plurality of quantum operation results; and computing, by the statistics computing circuit, a probability statistics associated with a Monte Carlo analysis from the plurality of random samples measured from the quantum operation results to obtain an average value.
    Type: Application
    Filed: June 1, 2023
    Publication date: June 27, 2024
    Applicant: Industrial Technology Research Institute
    Inventors: Yeong-Jar Chang, Jason Gemsun Young, Ying Wei Tseng
  • Patent number: 10978442
    Abstract: An electrostatic discharge (ESD) protection device and a method thereof are presented. A well is disposed in a substrate. A gate is disposed on the well. A source region and a drain region are located in the well and at two opposite sides of the gate respectively. A first doped region is located in the drain region, wherein the first doped region is electrically connected to the drain region. A second doped region is located in the source region, wherein the second doped region is electrically connected to the source region. A third doped region is located in the well and at a side of the drain region opposite to the gate. A fourth doped region is located in the well and at a side of the source region opposite to the gate, wherein the fourth doped region is electrically connected to the third doped region.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: April 13, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ying-Wei Tseng, Chun Chiang, Ping-Chen Chang, Tien-Hao Tang
  • Publication number: 20200381415
    Abstract: An electrostatic discharge (ESD) protection device and a method thereof are presented. A well is disposed in a substrate. A gate is disposed on the well. A source region and a drain region are located in the well and at two opposite sides of the gate respectively. A first doped region is located in the drain region, wherein the first doped region is electrically connected to the drain region. A second doped region is located in the source region, wherein the second doped region is electrically connected to the source region. A third doped region is located in the well and at a side of the drain region opposite to the gate. A fourth doped region is located in the well and at a side of the source region opposite to the gate, wherein the fourth doped region is electrically connected to the third doped region.
    Type: Application
    Filed: June 19, 2019
    Publication date: December 3, 2020
    Inventors: Ying-Wei Tseng, Chun Chiang, Ping-Chen Chang, Tien-Hao Tang
  • Patent number: 10522530
    Abstract: An electrostatic discharge (ESD) shielding semiconductor device and an ESD testing method thereof, the ESD shielding semiconductor device includes an integrated circuit, a seal ring and a conductive layer. The integrated circuit is disposed on a die, and the integrated circuit has a first region and a second region. The seal ring is disposed on the die to surround the integrated circuit. The conductive layer at least covers the first region, and which is electrically connected to the seal ring.
    Type: Grant
    Filed: March 21, 2018
    Date of Patent: December 31, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun Chiang, Ying-Wei Tseng, Ping-Chen Chang, Tien-Hao Tang
  • Publication number: 20190273077
    Abstract: An electrostatic discharge (ESD) shielding semiconductor device and an ESD testing method thereof, the ESD shielding semiconductor device includes an integrated circuit, a seal ring and a conductive layer. The integrated circuit is disposed on a die, and the integrated circuit has a first region and a second region. The seal ring is disposed on the die to surround the integrated circuit. The conductive layer at least covers the first region, and which is electrically connected to the seal ring.
    Type: Application
    Filed: March 21, 2018
    Publication date: September 5, 2019
    Inventors: Chun Chiang, Ying-Wei Tseng, Ping-Chen Chang, Tien-Hao Tang