Patents by Inventor Ying-Yang SU

Ying-Yang SU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230395562
    Abstract: Disclosed is a die-bonding method which provides a target substrate having a circuit structure with multiple electrical contacts and multiple semiconductor elements each semiconductor element having a pair of electrodes, arranges the multiple semiconductor elements on the target substrate with the pair of electrodes of each semiconductor element aligned with two corresponding electrical contacts of the target substrate, and applies at least one energy beam to join and electrically connect the at least one pair of electrodes of every at least one of the multiple semiconductor elements and the corresponding electrical contacts aligned therewith in a heating cycle by heat carried by the at least one energy beam in the heating cycle. The die-bonding method delivers scattering heated dots over the target substrate to avoid warpage of PCB and ensures high bonding strength between the semiconductor elements and the circuit structure of the target substrate.
    Type: Application
    Filed: August 15, 2023
    Publication date: December 7, 2023
    Applicant: EPISTAR CORPORATION
    Inventors: Min-Hsun HSIEH, Shih-An LIAO, Ying-Yang SU, Hsin-Mao LIU, Tzu-Hsiang WANG, Chi-Chih PU
  • Publication number: 20230335695
    Abstract: A light-emitting device includes a light-emitting element having a first-type semiconductor layer, a second-type semiconductor layer, an active stack between the first-type semiconductor layer and the second-type semiconductor layer, a bottom surface, and a top surface. A first electrode is disposed on the bottom surface and electrically connected to the first-type semiconductor layer. A second electrode is disposed on the bottom surface and electrically connected to the second-type semiconductor layer. A supporting structure is disposed on the top surface. The supporting structure has a thickness and a maximum width. A ratio of the maximum width to the thickness is of 2-150.
    Type: Application
    Filed: June 21, 2023
    Publication date: October 19, 2023
    Inventors: Min-Hsun HSIEH, Hsin-Mao LIU, Ying-Yang SU
  • Patent number: 11728310
    Abstract: Disclosed is a die-bonding method which provides a target substrate having a circuit structure with multiple electrical contacts and multiple semiconductor elements each semiconductor element having a pair of electrodes, arranges the multiple semiconductor elements on the target substrate with the pair of electrodes of each semiconductor element aligned with two corresponding electrical contacts of the target substrate, and applies at least one energy beam to join and electrically connect the at least one pair of electrodes of every at least one of the multiple semiconductor elements and the corresponding electrical contacts aligned therewith in a heating cycle by heat carried by the at least one energy beam in the heating cycle. The die-bonding method delivers scattering heated dots over the target substrate to avoid warpage of PCB and ensures high bonding strength between the semiconductor elements and the circuit structure of the target substrate.
    Type: Grant
    Filed: June 13, 2022
    Date of Patent: August 15, 2023
    Assignee: EPISTAR CORPORATION
    Inventors: Min-Hsun Hsieh, Shih-An Liao, Ying-Yang Su, Hsin-Mao Liu, Tzu-Hsiang Wang, Chi-Chih Pu
  • Patent number: 11710812
    Abstract: A light-emitting device includes a light-emitting element having a first-type semiconductor layer, a second-type semiconductor layer, an active stack between the first-type semiconductor layer and the second-type semiconductor layer, a bottom surface, and a top surface. A first electrode is disposed on the bottom surface and electrically connected to the first-type semiconductor layer. A second electrode is disposed on the bottom surface and electrically connected to the second-type semiconductor layer. A supporting structure is disposed on the top surface. The supporting structure has a thickness and a maximum width. A ratio of the maximum width to the thickness is of 2˜150.
    Type: Grant
    Filed: May 27, 2021
    Date of Patent: July 25, 2023
    Assignee: EPISTAR CORPORATION
    Inventors: Min-Hsun Hsieh, Hsin-Mao Liu, Ying-Yang Su
  • Publication number: 20230117490
    Abstract: A semiconductor element arrangement structure is provided. The semiconductor element arrangement structure includes a carrier substrate, first and second adhesive layers respectively disposed on the carrier substrate and separated from each other, and first and second semiconductor elements disposed on the first and second adhesive layers, respectively. The first semiconductor element has first and second electrodes on the same side of the first semiconductor element, and the second semiconductor element has third and fourth electrodes on the same side of the second semiconductor element. The first adhesive layer is in direct contact with the first and second electrodes, and the second adhesive layer is in direct contact with the third and fourth electrodes. The first adhesive layer has a first width between the first and second electrodes and has a second width not between the first and second electrodes that is less than the first width.
    Type: Application
    Filed: October 14, 2022
    Publication date: April 20, 2023
    Inventors: Chang-Tai HSIAO, Ying-Yang SU
  • Patent number: 11588084
    Abstract: Disclosed is a die-bonding method which provides a target substrate having a circuit structure with multiple electrical contacts and multiple semiconductor elements each semiconductor element having a pair of electrodes, arranges the multiple semiconductor elements on the target substrate with the pair of electrodes of each semiconductor element aligned with two corresponding electrical contacts of the target substrate, and applies at least one energy beam to join and electrically connect the at least one pair of electrodes of every at least one of the multiple semiconductor elements and the corresponding electrical contacts aligned therewith in a heating cycle by heat carried by the at least one energy beam in the heating cycle. The die-bonding method delivers scattering heated dots over the target substrate to avoid warpage of PCB and ensures high bonding strength between the semiconductor elements and the circuit structure of the target substrate.
    Type: Grant
    Filed: January 22, 2020
    Date of Patent: February 21, 2023
    Assignee: EPISTAR CORPORATION
    Inventors: Min-Hsun Hsieh, Shih-An Liao, Ying-Yang Su, Hsin-Mao Liu, Tzu-Hsiang Wang, Chi-Chih Pu
  • Patent number: 11530804
    Abstract: A light-emitting device includes a first light-emitting module, a second light-emitting module, a conductive layer and an insulation layer. The first light-emitting module includes a first substrate having a first cavity, a first sidewall, and a light-emitting component disposed on the first substrate. The second module includes a second substrate having a second cavity corresponding to the first cavity and a second sidewall corresponding to the first sidewall. The conductive layer is directly connected to the first cavity and the second cavity and electrically connect the first light-emitting module and the second light-emitting module. The insulation layer is directly connected to the first sidewall and the second sidewall.
    Type: Grant
    Filed: January 20, 2021
    Date of Patent: December 20, 2022
    Assignee: EPISTAR CORPORATION
    Inventors: Min-Hsun Hsieh, Ying-Yang Su, Shih-An Liao, Hsin-Mao Liu, Tzu-Hsiang Wang, Chi-Chih Pu
  • Publication number: 20220310555
    Abstract: Disclosed is a die-bonding method which provides a target substrate having a circuit structure with multiple electrical contacts and multiple semiconductor elements each semiconductor element having a pair of electrodes, arranges the multiple semiconductor elements on the target substrate with the pair of electrodes of each semiconductor element aligned with two corresponding electrical contacts of the target substrate, and applies at least one energy beam to join and electrically connect the at least one pair of electrodes of every at least one of the multiple semiconductor elements and the corresponding electrical contacts aligned therewith in a heating cycle by heat carried by the at least one energy beam in the heating cycle. The die-bonding method delivers scattering heated dots over the target substrate to avoid warpage of PCB and ensures high bonding strength between the semiconductor elements and the circuit structure of the target substrate.
    Type: Application
    Filed: June 13, 2022
    Publication date: September 29, 2022
    Applicant: EPISTAR CORPORATION
    Inventors: Min-Hsun HSIEH, Shih-An LIAO, Ying-Yang SU, Hsin-Mao LIU, Tzu-Hsiang WANG, Chi-Chih PU
  • Patent number: 11362060
    Abstract: Disclosed is a die-bonding method which provides a target substrate having a circuit structure with multiple electrical contacts and multiple semiconductor elements each semiconductor element having a pair of electrodes, arranges the multiple semiconductor elements on the target substrate with the pair of electrodes of each semiconductor element aligned with two corresponding electrical contacts of the target substrate, and applies at least one energy beam to join and electrically connect the at least one pair of electrodes of every at least one of the multiple semiconductor elements and the corresponding electrical contacts aligned therewith in a heating cycle by heat carried by the at least one energy beam in the heating cycle. The die-bonding method delivers scattering heated dots over the target substrate to avoid warpage of PCB and ensures high bonding strength between the semiconductor elements and the circuit structure of the target substrate.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: June 14, 2022
    Assignee: EPISTAR CORPORATION
    Inventors: Min-Hsun Hsieh, Shih-An Liao, Ying-Yang Su, Hsin-Mao Liu, Tzu-Hsiang Wang, Chi-Chih Pu
  • Publication number: 20210288232
    Abstract: A light-emitting device includes a light-emitting element having a first-type semiconductor layer, a second-type semiconductor layer, an active stack between the first-type semiconductor layer and the second-type semiconductor layer, a bottom surface, and a top surface. A first electrode is disposed on the bottom surface and electrically connected to the first-type semiconductor layer. A second electrode is disposed on the bottom surface and electrically connected to the second-type semiconductor layer. A supporting structure is disposed on the top surface. The supporting structure has a thickness and a maximum width. A ratio of the maximum width to the thickness is of 2˜150.
    Type: Application
    Filed: May 27, 2021
    Publication date: September 16, 2021
    Inventors: Min-Hsun HSIEH, Hsin-Mao LIU, Ying-Yang SU
  • Publication number: 20210222861
    Abstract: A light-emitting device includes a first light-emitting module, a second light-emitting module, a conductive layer and an insulation layer. The first light-emitting module includes a first substrate having a first cavity, a first sidewall, and a light-emitting component disposed on the first substrate. The second module includes a second substrate having a second cavity corresponding to the first cavity and a second sidewall corresponding to the first sidewall. The conductive layer is directly connected to the first cavity and the second cavity and electrically connect the first light-emitting module and the second light-emitting module. The insulation layer is directly connected to the first sidewall and the second sidewall.
    Type: Application
    Filed: January 20, 2021
    Publication date: July 22, 2021
    Inventors: Min-Hsun HSIEH, Ying-Yang SU, Shih-An LIAO, Hsin-Mao LIU, Tzu-Hsiang WANG, Chi-Chih PU
  • Patent number: 11024782
    Abstract: A light-emitting device includes a light-emitting element having a first-type semiconductor layer, a second-type semiconductor layer, an active stack between the first-type semiconductor layer and the second-type semiconductor layer, a bottom surface, and a top surface. A first electrode is disposed on the bottom surface and electrically connected to the first-type semiconductor layer. A second electrode is disposed on the bottom surface and electrically connected to the second-type semiconductor layer. A supporting structure is disposed on the top surface. The supporting structure has a thickness and a maximum width. A ratio of the maximum width to the thickness is of 2˜150.
    Type: Grant
    Filed: May 4, 2020
    Date of Patent: June 1, 2021
    Assignee: EPISTAR CORPORATION
    Inventors: Min-Hsun Hsieh, Hsin-Mao Liu, Ying-Yang Su
  • Publication number: 20200266177
    Abstract: A light-emitting device includes a light-emitting element having a first-type semiconductor layer, a second-type semiconductor layer, an active stack between the first-type semiconductor layer and the second-type semiconductor layer, a bottom surface, and a top surface. A first electrode is disposed on the bottom surface and electrically connected to the first-type semiconductor layer. A second electrode is disposed on the bottom surface and electrically connected to the second-type semiconductor layer. A supporting structure is disposed on the top surface. The supporting structure has a thickness and a maximum width. A ratio of the maximum width to the thickness is of 2˜150.
    Type: Application
    Filed: May 4, 2020
    Publication date: August 20, 2020
    Inventors: Min-Hsun HSIEH, Hsin-Mao LIU, Ying-Yang SU
  • Publication number: 20200243737
    Abstract: Disclosed is a die-bonding method which provides a target substrate having a circuit structure with multiple electrical contacts and multiple semiconductor elements each semiconductor element having a pair of electrodes, arranges the multiple semiconductor elements on the target substrate with the pair of electrodes of each semiconductor element aligned with two corresponding electrical contacts of the target substrate, and applies at least one energy beam to join and electrically connect the at least one pair of electrodes of every at least one of the multiple semiconductor elements and the corresponding electrical contacts aligned therewith in a heating cycle by heat carried by the at least one energy beam in the heating cycle. The die-bonding method delivers scattering heated dots over the target substrate to avoid warpage of PCB and ensures high bonding strength between the semiconductor elements and the circuit structure of the target substrate.
    Type: Application
    Filed: January 22, 2020
    Publication date: July 30, 2020
    Applicant: EPISTAR CORPORATION
    Inventors: Min-Hsun HSIEH, Shih-An LIAO, Ying-Yang SU, Hsin-Mao LIU, Tzu-Hsiang WANG, Chi-Chih PU
  • Publication number: 20200243478
    Abstract: Disclosed is a die-bonding method which provides a target substrate having a circuit structure with multiple electrical contacts and multiple semiconductor elements each semiconductor element having a pair of electrodes, arranges the multiple semiconductor elements on the target substrate with the pair of electrodes of each semiconductor element aligned with two corresponding electrical contacts of the target substrate, and applies at least one energy beam to join and electrically connect the at least one pair of electrodes of every at least one of the multiple semiconductor elements and the corresponding electrical contacts aligned therewith in a heating cycle by heat carried by the at least one energy beam in the heating cycle. The die-bonding method delivers scattering heated dots over the target substrate to avoid warpage of PCB and ensures high bonding strength between the semiconductor elements and the circuit structure of the target substrate.
    Type: Application
    Filed: August 27, 2019
    Publication date: July 30, 2020
    Applicant: EPISTAR CORPORATION
    Inventors: Min-Hsun HSIEH, Shih-An LIAO, Ying-Yang SU, Hsin-Mao LIU, Tzu-Hsiang WANG, Chi-Chih PU
  • Patent number: 10643980
    Abstract: A light-emitting device includes a light-emitting element, a supporting structure, a first wavelength conversion structure, and a light-absorbing layer. The light-emitting element includes a plurality of active stacks separated from each other, a first-type semiconductor layer continuously arranged on the plurality of active stacks, and a plurality of second-type semiconductor layers under the plurality of active stacks. The supporting structure is disposed on the light-emitting element and includes a first opening. The first wavelength conversion structure disposed in the first opening. The light-absorbing layer disposed on the top surface of the supporting structure.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: May 5, 2020
    Assignee: Epistar Corporation
    Inventors: Min-Hsun Hsieh, Hsin-Mao Liu, Ying-Yang Su
  • Publication number: 20190229098
    Abstract: A light-emitting device includes a light-emitting element, a supporting structure, a first wavelength conversion structure, and a light-absorbing layer. The light-emitting element includes a plurality of active stacks separated from each other, a first-type semiconductor layer continuously arranged on the plurality of active stacks, and a plurality of second-type semiconductor layers under the plurality of active stacks. The supporting structure is disposed on the light-emitting element and includes a first opening. The first wavelength conversion structure disposed in the first opening. The light-absorbing layer disposed on the top surface of the supporting structure.
    Type: Application
    Filed: January 22, 2019
    Publication date: July 25, 2019
    Inventors: Min-Hsun HSIEH, Hsin-Mao LIU, Ying-Yang SU