Abstract: Aspects of the invention include receiving an error code describing a computer hardware or firmware error. A list of data items to be collected to assist in correcting the error is received. The contents of the list are selected based at least in part on the error code and are in priority order. The data items in the list are collected and a buffer to store the collected data items is selected. At least a subset of the collected data items to be written is transmitted to the buffer. All of the collected data items are transmitted to the buffer when the buffer is large enough to hold all of the data items in the list. A subset of the collected data items are transmitted to the buffer in priority order when the buffer is not large enough to hold all of the data in the list.

Abstract: Aspects of the invention include receiving an error code describing a computer hardware or firmware error. A list of data items to be collected to assist in correcting the error is received. The contents of the list are selected based at least in part on the error code and are in priority order. The data items in the list are collected and a buffer to store the collected data items is selected. At least a subset of the collected data items to be written is transmitted to the buffer. All of the collected data items are transmitted to the buffer when the buffer is large enough to hold all of the data items in the list. A subset of the collected data items are transmitted to the buffer in priority order when the buffer is not large enough to hold all of the data in the list.

Abstract: Aspects of the invention include receiving an error code describing a computer hardware or firmware error. A list of data items to be collected to assist in correcting the error is built. The contents of the list are selected based at least in part on the error code and are in priority order. The data items in the list are collected and a buffer to store the collected data items is selected. At least a subset of the collected data items to be written is transmitted to the buffer. All of the collected data items are transmitted to the buffer when the buffer is large enough to hold all of the data items in the list. A subset of the collected data items are transmitted to the buffer in priority order when the buffer is not large enough to hold all of the data in the list.

Abstract: Aspects of the invention include receiving an error code describing a computer hardware or firmware error. A list of data items to be collected to assist in correcting the error is built. The contents of the list are selected based at least in part on the error code and are in priority order. The data items in the list are collected and a buffer to store the collected data items is selected. At least a subset of the collected data items to be written is transmitted to the buffer. All of the collected data items are transmitted to the buffer when the buffer is large enough to hold all of the data items in the list. A subset of the collected data items are transmitted to the buffer in priority order when the buffer is not large enough to hold all of the data in the list.

Abstract: Aspects of the present invention include a method, system and computer program product. The method includes a processor operating first and second physical channel identifier (PCHID) devices comprised of a plurality of functional logic components, wherein one or more of the functional logic components are specific to one or more of the first and second PCHIDs and wherein one or more of the functional logic components are in common and not specific to one or more of the first and second PCHIDs; determining that an error condition exists in the first PCHID or the second PCHID; and executing a recovery method to remove the error condition from the first PCHID or the second PCHID in which the error condition exists.

Abstract: Aspects of the present invention include a method, system and computer program product. The method includes a processor operating first and second physical channel identifier (PCHID) devices comprised of a plurality of functional logic components, wherein one or more of the functional logic components are specific to one or more of the first and second PCHIDs and wherein one or more of the functional logic components are in common and not specific to one or more of the first and second PCHIDs; determining that an error condition exists in the first PCHID or the second PCHID; and executing a recovery method to remove the error condition from the first PCHID or the second PCHID in which the error condition exists.

Abstract: Aspects of the present invention include a method, system and computer program product. The method includes a processor operating first and second physical channel identifier (PCHID) devices comprised of a plurality of functional logic components, wherein one or more of the functional logic components are specific to one or more of the first and second PCHIDs and wherein one or more of the functional logic components are in common and not specific to one or more of the first and second PCHIDs; determining that an error condition exists in the first PCHID or the second PCHID; executing a recovery method to remove the error condition from the first PCHID or the second PCHID in which the error condition exists; and executing, by the processor, an initialization method for both of the first and second PCHIDs.

Abstract: Aspects of the present invention include a method, system and computer program product. The method includes a processor operating first and second physical channel identifier (PCHID) devices comprised of a plurality of functional logic components, wherein one or more of the functional logic components are specific to one or more of the first and second PCHIDs and wherein one or more of the functional logic components are in common and not specific to one or more of the first and second PCHIDs; determining that an error condition exists in the first PCHID or the second PCHID; executing a recovery method to remove the error condition from the first PCHID or the second PCHID in which the error condition exists; and executing, by the processor, an initialization method for both of the first and second PCHIDs.

Abstract: Techniques are provided for performing automated operations to enable first-failure data capture functionality during initialization of multiple lockstep processors. Following a hardware reset of two lockstep processors, an indication is received of one or more crosscheck errors regarding the operation of the two lockstep processors. In response to the crosscheck errors, crosscheck first-failure data capture (FFDC) data is saved to one or more memory areas that are persistent across a hardware reset, and it is determined whether a predefined reset threshold has been satisfied. Responsive to determining that the predefined reset threshold has been satisfied, the crosscheck FFDC data from the one or more persistent memory areas is analyzed and one or more crosscheck initialization codes are responsively generated. An additional hardware reset is initiated.

Abstract: Techniques are provided for performing automated operations to enable first-failure data capture functionality during initialization of multiple lockstep processors. Following a hardware reset of two lockstep processors, an indication is received of one or more crosscheck errors regarding the operation of the two lockstep processors. In response to the crosscheck errors, crosscheck first-failure data capture (FFDC) data is saved to one or more memory areas that are persistent across a hardware reset, and it is determined whether a predefined reset threshold has been satisfied. Responsive to determining that the predefined reset threshold has been satisfied, the crosscheck FFDC data from the one or more persistent memory areas is analyzed and one or more crosscheck initialization codes are responsively generated. An additional hardware reset is initiated.

Abstract: Examples of techniques for transparent north port recovery of an error in an input/output device are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include: detecting, by a processing device, a command timeout; sending, by the processing device, an input/output (I/O) error signal to a host processing system connected to the hardware device via a north port of the hardware device; terminating, by the host processing system, a link between the north port of the hardware device and the host processing system; enabling, by the processing device, halt command forwarding on the hardware device; halting, by the processing device, commands upon detecting the halt command forwarding; and resetting, by the processing device, the link between the north port of the hardware device and the host processing system.

Abstract: The emulation of a data processing I/O protocol employs a process which obviates the need to consider hardware specific functionality for which emulation is not an optimal solution. The particular protocol described in exemplary fashion herein is the OSA protocol as defined by Open System Adapter standards. The use of this emulation is also seen to leave in place all of the software tools otherwise employed.

Abstract: The emulation of a data processing I/O protocol employs a process which obviates the need to consider hardware specific functionality for which emulation is not an optimal solution. The particular protocol described in exemplary fashion herein is the OSA protocol as defined by Open System Adapter standards. The use of this emulation is also seen to leave in place all of the software tools otherwise employed.

Abstract: The emulation of a data processing I/O protocol employs a process which obviates the need to consider hardware specific functionality for which emulation is not an optimal solution. The particular protocol described in exemplary fashion herein is the OSA protocol as defined by Open System Adapter standards. The use of this emulation is also seen to leave in place all of the software tools otherwise employed.

Abstract: An article of manufacture, method and system are provided for facilitating input/output (I/O) processing of at least one guest processing system. The article of manufacture includes at least one computer-usable medium having computer-readable program code logic to facilitate the I/O processing of the at least one guest processing system. The computer-readable program code logic when executing performing the following: emulating on a native system an I/O architecture for the at least one guest processing system, the emulating including: providing multiple device managers for a plurality of I/O devices of the I/O architecture; providing at least one communications adapter process interfacing the multiple device managers to the at least one network driver process; and wherein the multiple device managers translate I/O messages in at least one guest processing system format to messages in native system format for processing by the at least one communications adapter process, thereby facilitating I/O processing.

Abstract: The emulation of a data processing I/O protocol employs a process which obviates the need to consider hardware specific functionality for which emulation is not an optimal solution. The particular protocol described in exemplary fashion herein is the OSA protocol as defined by Open System Adapter standards. The use of this emulation is also seen to leave in place all of the software tools otherwise employed.

Abstract: An article of manufacture, method and system are provided for facilitating input/output (I/O) processing of at least one guest processing system. The article of manufacture includes at least one computer-usable medium having computer-readable program code logic to facilitate the I/O processing of the at least one guest processing system. The computer-readable program code logic when executing performing the following: emulating on a native system an I/O architecture for the at least one guest processing system, the emulating including: providing multiple device managers for a plurality of I/O devices of the I/O architecture; providing at least one communications adapter process interfacing the multiple device managers to the at least one network driver process; and wherein the multiple device managers translate I/O messages in at least one guest processing system format to messages in native system format for processing by the at least one communications adapter process, thereby facilitating I/O processing.