Abstract: A master/slave system conforming to an I2C communication protocol includes a master, an I2C bus, a power supply module, an independent slave and a plurality of dependent slaves. The master is configured to generate a data signal and a clock signal, the data signal including address information and a plurality of control instructions. The power supply module is configured to provide constant voltage power in a high potential state to the I2C bus. The independent slave is provided with a device address and is configured to receive the data signal and the clock signal according to the device address, the address information and the control instructions. The plurality of dependent slaves are connected in series with one another through a plurality of buses and are electrically connected to the independent slave, the potential state of each bus in idle is different from that of the I2C bus in idle.

Abstract: The present invention discloses a method of to generate transaction ID(s) in a bus interconnection design. An encoding table for each slave can be derived by calculating all possible transactions from all the masters to the slave so as to determine the minimum width of the transaction ID received by the slave in the interconnecting bus design, thereby avoiding the routing congestion in the interconnecting bus.

Abstract: The present invention discloses a method of to generate transaction ID(s) in a bus interconnection design. An encoding table for each slave can be derived by calculating all possible transactions from all the masters to the slave so as to determine the minimum width of the transaction ID received by the slave in the interconnecting bus design, thereby avoiding the routing congestion in the interconnecting bus.