Abstract: The system and methods described herein are directed to monitoring and tracking surgical instruments through sterilization processing. Imaging methods described are performed based on a variety of needs such as to monitor damage, wear, and biomass. Also described are how automation, vision augmentation, and data management systems can be incorporated into the system to facilitate monitoring and tracking. The system and methods described here will use specialized optical imaging methods together with automation and image analysis methods to perform inspection and tracking of surgical instruments faster, more accurately, and less expensively than using existing methods. The new imaging methods disclosed include ultraviolet fluorescence, polarization imaging, oblique illumination, and extensive light source in reflection. Further, the methods include using multiple imaging methods and imaging methods in combination with automation and imaging processing for assessing surgical instruments.

Abstract: A circuit comprises scan gating devices inserted between outputs of scan chains and inputs of a test response compactor. The scan gating devices divides the scan chains into groups of scan chains. Each of the scan gating devices operates in either an enabled mode or a disenabled mode based on a first signal. A scan gating device operating in the enabled mode blocks, blocks only at some clock cycles, or does not block a portion of a test response of a test pattern captured by and outputted from a scan chain in the associated scan chain group based on a second signal. Scan gating devices operating in the disenabled mode do not block, or based on a third signal, either block or do not block, a portion of the test response captured by and outputted from all scan chains in each of the associated scan chain groups.

Abstract: A system for testing a circuit comprises scan chains, a controller configured to generate a bit-inverting signal based on child test pattern information, and bit-inverting circuitry coupled to the controller and configured to invert bits of a parent test pattern associated with a plurality of shift clock cycles based on the bit-inverting signal to generate a child test pattern during a shift operation. Here, the plurality of shift clock cycles for bit inverting occur every m shift clock cycles, and the child test pattern information comprises information of m and location of the plurality of shift clock cycles in the shift operation.

Abstract: A circuit comprises scan gating devices inserted between outputs of scan chains and inputs of a test response compactor. The scan gating devices divides the scan chains into groups of scan chains. Each of the scan gating devices operates in either an enabled mode or a disenabled mode based on a first signal. A scan gating device operating in the enabled mode blocks, blocks only at some clock cycles, or does not block a portion of a test response of a test pattern captured by and outputted from a scan chain in the associated scan chain group based on a second signal. Scan gating devices operating in the disenabled mode do not block, or based on a third signal, either block or do not block, a portion of the test response captured by and outputted from all scan chains in each of the associated scan chain groups.

Abstract: A system for testing a circuit comprises scan chains, a controller configured to generate a bit- inverting signal based on child test pattern information, and bit-inverting circuitry coupled to the controller and configured to invert bits of a parent test pattern associated with a plurality of shift clock cycles based on the bit-inverting signal to generate a child test pattern during a shift operation. Here, the plurality of shift clock cycles for bit inverting occur every m shift clock cycles, and the child test pattern information comprises information of m and location of the plurality of shift clock cycles in the shift operation.