Abstract: Provided are an Electro Static Discharge (ESD) circuit and a memory. The ESD circuit includes: a detection circuit and multiple electrostatic discharge circuits. The detection circuit includes at least one sub-detection circuit connected between a first power end and a second power end. Each sub-detection circuit generates a sub-trigger signal based on a voltage change between the first power end and the second power end. The multiple electrostatic discharge circuits are connected between the first power end and the second power end. The multiple electrostatic discharge circuits are configured to be turned on according to the one or more sub-trigger signals.

Abstract: Embodiments relates to a layout structure and a method for fabricating the same. A frequency divider pattern layer includes a first frequency divider region, a second frequency divider region, a third frequency divider region and a fourth frequency divider region arranged centrosymmetrically. A conductor pattern layer includes a first sub-conductor pattern layer and a second sub-conductor pattern layer stacked. The first sub-conductor pattern layer is configured to communicate the first frequency divider region with the second frequency divider region, and communicate the third frequency divider region with the fourth frequency divider region. The second sub-conductor pattern layer is configured to communicate the first frequency divider region with the fourth frequency divider region, and communicate the second frequency divider region with the third frequency divider region. The embodiments reduce a channel transmission difference between different frequency dividers in a frequency divider structure.

Abstract: A package structure includes N first pads, N redistribution layers, second pads and third pads. Each first pad is formed by a interconnect layer exposed by one via hole. Each redistribution layer covers the isolation layer and is electrically connected with a corresponding first pad. Some first pads are arranged side by side along a first direction near a first edge of the semiconductor functional structure, and other first pads are arranged side by side along the first direction near a second edge of the semiconductor functional structure. The exposed parts of each redistribution layer form a second and a third pad. Both an offset direction and an offset distance between a center point of the second pad and that of a corresponding first pad are same. A relative position between the second pad and the third pad for some redistribution layers is different from that for others.

Abstract: The present disclosure relates to a clock tree layout and a forming method thereof. The clock tree layout includes: a divider module layout, a phase module layout and a wire pattern layer. The divider module layout is configured to receive a first clock signal, and divide the first clock signal, and obtain a plurality of second clock sampling signals phase-associated; the phase module layout includes a first quantity of phase modules disposed in a first preset direction, the phase module is configured to generate a second clock signal based on a correspondingly connected second clock sampling signal, and the phase modules are symmetrically distributed with respect to the divider module layout; the wire pattern layer is configured to electrically connect the phase module and a divider module in the divider module layout; a difference between phases of any two of the second clock signals falls within a preset precision range.

Abstract: The integrated circuit layout includes: a data pad; an electro-static discharge circuit, located at one side of the data pad and electrically connected to the data pad; a first transmission circuit, located at a side of the electro-static discharge circuit which faces towards the data pad, wherein the first transmission circuit is electrically connected to the electro-static discharge circuit through a first bus; a second transmission circuit, located at a side of the electro-static discharge circuit which is away from the first transmission circuit, wherein the second transmission circuit is electrically connected to the electro-static discharge circuit through a second bus. One of the first transmission circuit and the second transmission circuit is configured to transmit data from the data pad to a memory array, and the other is configured to receive data from the memory array and transmit the data to the data pad.