Patents by Inventor Ying Ern Ho

Ying Ern Ho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11955436
    Abstract: Embodiments include package substrates and method of forming the package substrates. A package substrate includes a dielectric over a conductive layer, and a conductive line on the dielectric. The package substrate includes a plurality of conductive bumps on a surface of the conductive line, where the conductive bumps are conductively coupled to the conductive line, and a solder resist over the conductive line and the dielectric. The surface of the conductive line may be a bottom surface, where the conductive bumps are below the conductive line and conductively coupled to the bottom surface of the conductive line, and where the conductive bumps may be embedded in the dielectric. The surface of the conductive line may be a top surface, where the conductive bumps are above the conductive line and conductively coupled to the top surface of the conductive line, and wherein the conductive bumps are embedded in the solder resist.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: April 9, 2024
    Assignee: Intel Corporation
    Inventors: Khang Choong Yong, Ying Ern Ho, Yun Rou Lim, Wil Choon Song, Stephen Hall
  • Publication number: 20230396025
    Abstract: A magnetic grounding technique implements a magnet assembly. The magnet assembly may be soldered to a component to facilitate grounding of a metal shield layer of a cable assembly. A cable plating may be plated onto an exposed part of the insulator of a cable assembly to form the cable assembly, and which galvanically contacts the metal shield layer of the cable assembly. The cable plating may comprise an electrically conductive and magnetic material to ensure magnetic attraction with the magnet assembly. The magnetic assembly is thus magnetically attracted to the cable plating, and also provides galvanic contact between the cable plating and, in turn, the metal shield layer of the cable and ground to reduce RFI. The magnet assembly also magnetically aligns the cable connection pins with those of a mating connector, thus reducing the strain placed on the connectors.
    Type: Application
    Filed: August 23, 2023
    Publication date: December 7, 2023
    Inventors: Ying Ern Ho, Boon Ping Koh, Ya Yeing Lo, Luqman Al-Hakim Mohd Nasran, Ameera Wahida Solikhudin
  • Patent number: 11729900
    Abstract: Apparatuses and methods are provided for mitigating radio frequency interference and electromagnetic compatibility issues caused by the resonance of metal planes of a circuit board. A method for controlling impedance at an edge of a circuit board includes creating a cut at an edge of a plane of the circuit board. The cut extends from the edge of the plane to a point at a depth into the plane. The method can further include creating a cut pattern in the edge of the plane by repeating the cut along the edge of the plane such that an impedance of the plane at the depth is different, or lower, than an impedance of the plane at the edge of the plane. Other aspects are described.
    Type: Grant
    Filed: March 14, 2022
    Date of Patent: August 15, 2023
    Assignee: Intel Corporation
    Inventors: Stephen Harvey Hall, Khang Choong Yong, Ying Ern Ho, Yun Rou Lim, Wil Choon Song
  • Publication number: 20220304143
    Abstract: Apparatuses and methods are provided for mitigating radio frequency interference and electromagnetic compatibility issues caused by the resonance of metal planes of a circuit board. A method for controlling impedance at an edge of a circuit board includes creating a cut at an edge of a plane of the circuit board. The cut extends from the edge of the plane to a point at a depth into the plane. The method can further include creating a cut pattern in the edge of the plane by repeating the cut along the edge of the plane such that an impedance of the plane at the depth is different, or lower, than an impedance of the plane at the edge of the plane. Other aspects are described.
    Type: Application
    Filed: March 14, 2022
    Publication date: September 22, 2022
    Inventors: Stephen Harvey Hall, Khang Choong Yong, Ying Ern Ho, Yun Rou Lim, Wil Choon Song
  • Patent number: 11277903
    Abstract: Apparatuses and methods are provided for mitigating radio frequency interference and electromagnetic compatibility issues caused by the resonance of metal planes of a circuit board. A method for controlling impedance at an edge of a circuit board includes creating a cut at an edge of a plane of the circuit board. The cut extends from the edge of the plane to a point at a depth into the plane. The method can further include creating a cut pattern in the edge of the plane by repeating the cut along the edge of the plane such that an impedance of the plane at the depth is different, or lower, than an impedance of the plane at the edge of the plane. Other aspects are described.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: March 15, 2022
    Assignee: Intel Corporation
    Inventors: Stephen Harvey Hall, Khang Choong Yong, Ying Ern Ho, Yun Rou Lim, Wil Choon Song
  • Publication number: 20210191512
    Abstract: Apparatus, systems, articles of manufacture, and methods for adaptive display control in virtual reality environments are disclosed. An example virtual reality display device for adaptive display control in a virtual reality environment includes memory and a processor to execute instructions to detect a first pupil size after a predetermined amount of time, determine a characteristic of a display image, identify a second pupil size from a plurality of pupil sizes correlated with the characteristic of the display image, perform a comparison of the first pupil size and the second pupil size, determine a margin of difference between the first pupil size and the second pupil size, and adjust the characteristic of the display image to change the first pupil size and reduce the margin difference.
    Type: Application
    Filed: March 8, 2021
    Publication date: June 24, 2021
    Inventors: Ying Ern Ho, Wooi Jou Tan, Natasya Athirah Abdul Khalid
  • Patent number: 10942565
    Abstract: Apparatus, systems, articles of manufacture, and methods for adaptive display control in virtual reality environments are disclosed. An example virtual reality display device for adaptive display control in a virtual reality environment includes a scanner to detect a first size of a pupil of an eye of a user. The device also includes an analyzer to determine a first characteristic of a display image, reference a second pupil size based on the first characteristic of the display image, compare the first pupil size and the second pupil size, and adjust a second characteristic of the display image when the second pupil size is different than the first pupil size. The device also includes a display screen to present the second characteristic.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: March 9, 2021
    Assignee: Intel Corporation
    Inventors: Ying Ern Ho, Wooi Jou Tan, Natasya Athirah Abdul Khalid
  • Publication number: 20200343194
    Abstract: Embodiments include package substrates and method of forming the package substrates. A package substrate includes a dielectric over a conductive layer, and a conductive line on the dielectric. The package substrate includes a plurality of conductive bumps on a surface of the conductive line, where the conductive bumps are conductively coupled to the conductive line, and a solder resist over the conductive line and the dielectric. The surface of the conductive line may be a bottom surface, where the conductive bumps are below the conductive line and conductively coupled to the bottom surface of the conductive line, and where the conductive bumps may be embedded in the dielectric. The surface of the conductive line may be a top surface, where the conductive bumps are above the conductive line and conductively coupled to the top surface of the conductive line, and wherein the conductive bumps are embedded in the solder resist.
    Type: Application
    Filed: April 24, 2019
    Publication date: October 29, 2020
    Inventors: Khang Choong YONG, Ying Ern HO, Yun Rou LIM, Wil Choon SONG, Stephen HALL
  • Publication number: 20200314999
    Abstract: Apparatuses and methods are provided for mitigating radio frequency interference and electromagnetic compatibility issues caused by the resonance of metal planes of a circuit board. A method for controlling impedance at an edge of a circuit board includes creating a cut at an edge of a plane of the circuit board. The cut extends from the edge of the plane to a point at a depth into the plane. The method can further include creating a cut pattern in the edge of the plane by repeating the cut along the edge of the plane such that an impedance of the plane at the depth is different, or lower, than an impedance of the plane at the edge of the plane. Other aspects are described.
    Type: Application
    Filed: March 28, 2019
    Publication date: October 1, 2020
    Inventors: Stephen Harvey Hall, Khang Choong Yong, Ying Ern Ho, Yun Rou Lim, Wil Choon Song
  • Publication number: 20200314998
    Abstract: Embodiments herein relate to systems, apparatuses, processes or techniques directed to an impedance cushion coupled with a power plane to provide voltage for a system, where the impedance cushion is dimensioned to suppress resonance of the power plane to mitigate RFI or EMI emanating from the power plane during operation.
    Type: Application
    Filed: March 29, 2019
    Publication date: October 1, 2020
    Inventors: Khang Choong YONG, Ying Ern HO, Wil Choon SONG, Yun Rou LIM, Telesphor KAMGAING
  • Patent number: 10779402
    Abstract: A printed circuit board (PCB) includes a dielectric plane and a ground plane parallel to and spaced apart from the dielectric plane. The dielectric plane includes a pair of signal traces and a 3-dimensional (3D) grounded (GND) fence located between the pair of signal traces. The 3D GND fence is electrically connected to the ground plane, and protrudes perpendicularly from the dielectric plane. The 3D GND fence is located equidistant from each of the pair of signal traces, and the 3D GND fence is configured to block electromagnetic interference (EMI) from a first of the pair of signal traces to a second of the pair of the signal traces. The pair of signal traces is configured to form part of a noise-sensitive electronic circuit. The 3D GND fence may have a rectangular configuration.
    Type: Grant
    Filed: May 3, 2019
    Date of Patent: September 15, 2020
    Assignee: Intel Corporation
    Inventors: Kai Chong Ng, Natasya Athirah Abdul Khalid, Florence Su Sin Phun, Yee Hung See Tau, Asmah Truky, Ying Ern Ho
  • Publication number: 20190265785
    Abstract: Apparatus, systems, articles of manufacture, and methods for adaptive display control in virtual reality environments are disclosed. An example virtual reality display device for adaptive display control in a virtual reality environment includes a scanner to detect a first size of a pupil of an eye of a user. The device also includes an analyzer to determine a first characteristic of a display image, reference a second pupil size based on the first characteristic of the display image, compare the first pupil size and the second pupil size, and adjust a second characteristic of the display image when the second pupil size is different than the first pupil size. The device also includes a display screen to present the second characteristic.
    Type: Application
    Filed: December 17, 2018
    Publication date: August 29, 2019
    Inventors: Ying Ern Ho, Wooi Jou Tan, Natasya Athirah Abdul Khalid
  • Patent number: 10134690
    Abstract: Embodiments herein may relate to a package with one or more layers. A silicon die may be coupled with the one or more layers via an adhesive. A package stiffener may also be coupled with the adhesive adjacent to the die. A magnetic thin film may be coupled with the package stiffener. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: November 20, 2018
    Assignee: INTEL CORPORATION
    Inventors: Hao-Han Hsu, Ying Ern Ho, Jaejin Lee
  • Publication number: 20180122748
    Abstract: Embodiments herein may relate to a package with one or more layers. A silicon die may be coupled with the one or more layers via an adhesive. A package stiffener may also be coupled with the adhesive adjacent to the die. A magnetic thin film may be coupled with the package stiffener. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: October 27, 2016
    Publication date: May 3, 2018
    Inventors: Hao-Han Hsu, Ying Ern Ho, Jaejin Lee