Patents by Inventor Yingging Cui
Yingging Cui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12369476Abstract: The present disclosure provides a transparent display panel and method for manufacturing the same and a display device. The transparent display panel includes pixel units arranged in an array, and the pixel unit includes a light-emitting area and a transparent area. The pixel unit includes a pixel defining layer disposed in the light-emitting area and defining a plurality of opening areas. A light-emitting device is disposed in the opening area. The pixel unit further includes a transparent film layer disposed in the transparent area and being of a hydrophobic material. The transparent film layer includes a groove and an inclined channel, and the channel connects the groove with any one of the opening areas. A bottom surface of the groove is higher than a bottom surface of the opening area, and an area of the groove is greater than that of the opening area connected with the channel.Type: GrantFiled: April 20, 2021Date of Patent: July 22, 2025Assignee: BOE TECHNOLOGY GROUP CO., LTD.Inventor: Ying Cui
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Publication number: 20250232816Abstract: A memory device includes word lines and a control circuit coupled to the word lines. The control circuit is configured to apply a programming voltage to a first word line of the word lines, apply a first pass voltage to a second word line of the word lines, apply a second pass voltage to a third word lines of the word lines, the second word line and the third word line are located on opposite sides of the first word line, apply a third pass voltage to a fourth word line of the word lines, the second word line is located between the fourth word line and the first word line, and apply a fourth pass voltage to a fifth word line of the word lines. The third word line is located between the fifth word line and the first word line. The first pass voltage is different from the third pass voltage. The second pass voltage is different from the fourth pass voltage.Type: ApplicationFiled: February 18, 2025Publication date: July 17, 2025Inventors: Jie YUAN, Ying CUI, Yuanyuan MIN, YaLi SONG, HongTao LIU
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Publication number: 20250174277Abstract: In certain aspects, a memory device includes memory strings each including a drain select gate (DSG) transistor, memory cells, and a source select gate (SSG) transistor, and a peripheral circuit coupled to the memory strings. The peripheral circuit is configured to, in a program operation, program a select memory cell of the memory cells in a select memory string of the memory strings, and inhibit an unselect memory cell of the memory cells in an unselect memory string of the memory strings. The peripheral circuit includes a word line driver configured to in a pre-pulse period and a post-pulse period in a first loop of the program operation, turn off the DSG transistor in the unselect memory string, and in at least one of a pre-pulse period or a post-pulse period in a second loop of the program operation after the first loop, turn on the DSG transistor in the unselect memory string.Type: ApplicationFiled: December 29, 2023Publication date: May 29, 2025Inventors: Yuanyuan Min, Kaikai You, Ying Cui, Jianquan Jia, Xiangnan Zhao
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Patent number: 12279501Abstract: An array substrate is provided, including: multiple columns of pixel units on a substrate, including multiple first and second pixel unit columns alternately in a row direction; each first/second pixel unit column includes multiple first/second pixel units in a column direction; first and second pixel units adjacent to each other are staggered in the row direction in adjacent first and second pixel unit columns. Each first/second pixel unit includes at least two sub-pixels of different colors in multiple columns, and each column of sub-pixels have a same color; each first/second pixel unit includes one rectangular sub-pixel and at least one non-rectangular sub-pixel on opposite first and/or second sides of the rectangular sub-pixel and having a first side opposite to a long side and/or a width of the rectangular sub-pixel, and an orthographic projection of the non-rectangular sub-pixel on the first side is within the first side.Type: GrantFiled: December 20, 2021Date of Patent: April 15, 2025Assignee: BOE TECHNOLOGY GROUP CO., LTD.Inventor: Ying Cui
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Publication number: 20250113705Abstract: Provided are a display substrate and a display device. The display substrate includes a driving transistor and a storage capacitor, the storage capacitor includes a first electrode plate and a second electrode plate, the second electrode plate is arranged in a same layer as the channel of the driving transistor, the second electrode plate is closer to the base substrate than the first electrode plate, an orthographic projection of the second electrode plate on the base substrate overlaps with an orthographic projection of the pixel opening on the base substrate, the display substrate satisfies a following relationship: a value range of (W*L+S2)*M1/M2 is [0.014, 0.133], and a value range of S2/(W*L) is [2.82, 28.Type: ApplicationFiled: November 17, 2022Publication date: April 3, 2025Inventors: Tong WU, Hongli WANG, Pan LI, Ying HAN, Ying CUI, Can YUAN, Xing ZHANG, Ruqin ZHANG, Chunping LONG
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Patent number: 12260096Abstract: The present disclosure provides a three-dimensional NAND memory device, comprising a NAND string including a memory cell to be inhibited to program, a word line driver, and a controller configured to control the word line driver to perform a programming operation on the memory cell controlled by a selected word line of a plurality of word lines including a first unselected word line adjacent to the selected word line, a first plurality of unselected word lines adjacent to the first unselected word line, and a second plurality of unselected word lines adjacent to the first plurality of unselected word lines. The programming operation includes applying a programming voltage signal to the selected word line; applying a first pass voltage to the first plurality of unselected word lines; and applying a second pass voltage to the second plurality of unselected word lines, the first pass voltage is different from the second pass voltage.Type: GrantFiled: November 10, 2022Date of Patent: March 25, 2025Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Jie Yuan, Ying Cui, Yuanyuan Min, YaLi Song, HongTao Liu
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Publication number: 20250095715Abstract: A non-volatile memory device and a control method are provided e disclosed. The non-volatile memory device includes a memory array, a bit line, a plurality of word lines, a first control circuit, and second control circuit. The bit line is connected to a first memory string of the memory array. The plurality of word lines are connected to memory cells of the first memory string and each word line is connected to a respective memory cell. The first control circuit is configured to apply a bit line pre-pulse signal to the bit line during a pre-charge period. The second control circuit is configured to apply a word line signal to a selected word line and apply a plurality of word line pre-pulse signals to word lines disposed between a select gate line and the selected word line. Voltage levels of the plurality of word line pre-pulse signals are incremental.Type: ApplicationFiled: November 29, 2024Publication date: March 20, 2025Inventors: Jianquan Jia, Ying Cui, Kaikai You
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Publication number: 20250089513Abstract: A display substrate, a manufacturing method therefor, and a display device. The display substrate includes: a base substrate; a light-emitting substrate disposed on the base substrate and the light-emitting substrate being configured to emit incident light; a color conversion layer disposed at a side of the light emitting substrate away from the base substrate and the color conversion layer being configured to convert the incident light emitted from the light emitting substrate into light of a specific color; a selective reflection layer disposed on a side of the color conversion layer away from the base substrate and the selective reflection layer being configured to reflect incident light not converted by the color conversion layer to the color conversion layer and to transmit light of the specific color converted by the color conversion layer.Type: ApplicationFiled: February 28, 2023Publication date: March 13, 2025Inventors: Ying CUI, Donghui YU, Cheng XU, Dandan ZHOU
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Publication number: 20250078928Abstract: A memory device includes a first select line coupled to a first select transistor, a second select line coupled to a second select transistor, a word line coupled to a memory cell and located between the first select line and the second select line, and a peripheral circuit coupled to the first select line, the second select line, and the word line. The peripheral circuit is configured to apply a first voltage to the first select line to pre-program the first select transistor at a first time point in a first phase during an erasing operation. A voltage of the first select line at a second time point in a second phase after the first phase during the erasing operation is a second voltage greater than the first voltage. A voltage of the word line in the second phase during the erasing operation is a third voltage lower than the first voltage.Type: ApplicationFiled: November 20, 2024Publication date: March 6, 2025Inventors: Zhipeng Dong, Ying Cui, Li Xiang
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Publication number: 20250069955Abstract: This application discloses a method for analyzing a wafer angle in semiconductor integrated circuit manufacturing, including step 1: collecting machine angle data; step 2: predicting and forming an angle trajectory map of each analyzed wafer in a process according to the machine angle data; step 3: performing first grouping on defective wafers in an analyzed lot according to defect types; step 4: selecting one first group as a selected group, and performing second grouping on each defective wafer in the selected group according to defect directions; and step 5: calculating a direction difference between defect directions of second groups, and determining a site and a machine where a defect occurs in combination with the direction difference and an angle difference in the angle trajectory map of each detective wafer in the selected group. This application further discloses a system for analyzing a wafer angle in semiconductor integrated circuit manufacturing.Type: ApplicationFiled: September 14, 2023Publication date: February 27, 2025Applicant: Shanghai Huali Microelectronics CorporationInventor: Ying Cui
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Publication number: 20250068558Abstract: The present disclosure provides a method for operating a memory, a memory and a memory system, and relates to the technical field of semiconductor chip. The method includes: during the erase phase, applying an erase voltage to the word line, and applying an erase voltage to the select line coupled to a target select gate; during the program phase for select gate, applying a pass voltage to the word line, and applying a program voltage to the select line coupled to the target select gate.Type: ApplicationFiled: December 4, 2023Publication date: February 27, 2025Inventors: Jianquan JIA, XiangNan ZHAO, Yuanyuan MIN, Ying CUI, Kaikai YOU, Chenhui LI, Wei QI, Jiameng CUI, Lei GUAN, Junbao WANG, Lei JIN
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Publication number: 20250069662Abstract: The present disclosure provides a memory device, a memory system, and an operation method of a memory device, and relates to the technical field of semiconductor chips. The memory device includes a memory cell array including a source layer, a bottom select gate layer, and a gate layer, and the bottom select gate layer is located between the source layer and the gate layer, wherein the bottom select gate layer includes a plurality of bottom select gates, and a bottom select gate of a first memory string and a bottom select gate of a second memory string are connected with a same select line; and a peripheral circuit coupled to the memory cell array, wherein the peripheral circuit is configured to apply a selection voltage to the select line to control the first memory string and the second memory string.Type: ApplicationFiled: December 18, 2023Publication date: February 27, 2025Inventors: Jianquan JIA, XiangNan ZHAO, Feng XU, Yuanyuan MIN, Ying CUI, Chenhui LI, Wei QI, Junbao WANG, Lei JIN
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Publication number: 20250069673Abstract: According to one aspect, a method of operating a memory is provided. The method may include applying a first power supply voltage to a common source during a program precharge process. The method may include applying a first voltage to a first bottom gate line and applying a second voltage to a second bottom gate line starting at a first moment of the program precharge process. The method may include applying a second power supply voltage to the first bottom gate line and applying a third voltage to the second bottom gate line after the first moment of the program precharge process.Type: ApplicationFiled: December 15, 2023Publication date: February 27, 2025Inventors: Junbao Wang, Jianquan Jia, Yuanyuan Min, Xiangnan Zhao, Ying Cui, Kaikai You, Jiameng Cui, Lei Guan, Chenhui Li, An Zhang, Lei Jin
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Patent number: 12237025Abstract: A memory device, a memory system, and a program operation method are disclosed. In one example, at an ith programming loop, in response to determining that index i is greater than or equal to a first preset value and less than an initial verification loop number corresponding to a target state of memory cells in the memory device, an ith programming inhibition operation may be performed on the memory cells of the target state. Index i may be a positive integer, and the initial verification loop number may indicate a programming loop number that starts a verification operation corresponding to the target state of the memory cells.Type: GrantFiled: February 23, 2023Date of Patent: February 25, 2025Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventors: Yali Song, Xiangnan Zhao, Ying Cui
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Patent number: 12238974Abstract: A display substrate includes a base substrate, a plurality of first electrodes, a first pixel defining layer, and a second pixel defining layer disposed on the base substrate, and light-emitting layers disposed in a plurality of second opening regions. The first pixel defining layer includes a plurality of first opening regions, and each of the first opening regions exposes at least a portion of a first electrode. The second pixel defining layer includes the plurality of second opening regions, each second opening regions corresponds to at least two first opening regions, and the orthogonal projections of the at least two first opening regions on the base substrate are located within the orthogonal projection of the second opening region on the base substrate. The light-emitting layers overspreads the plurality of second opening regions in a plane perpendicular to a thickness direction of the base substrate, respectively.Type: GrantFiled: February 18, 2021Date of Patent: February 25, 2025Assignee: BOE TECHNOLOGY GROUP CO., LTD.Inventor: Ying Cui
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Publication number: 20250054539Abstract: A memory device includes memory cells, word lines respectively coupled to the memory cells, bit lines respectively coupled to the memory cells, and a peripheral circuit coupled to the word lines and the bit lines. The peripheral circuit is configured to apply a first program voltage to a first word line of the word lines, after applying the first program voltage to the first word line, apply a second program voltage to a second word line of the word lines, and after applying the second program voltage to the second word line, perform a program pre-charge operation. To perform the pre-charge operation, a first voltage is applied to the second word line, a second voltage is applied to the first word line, and after the program pre-charge operation, a third program voltage is applied to the first word line. The first voltage is greater than the second voltage.Type: ApplicationFiled: October 31, 2024Publication date: February 13, 2025Inventors: Ying Cui, Jianquan Jia, Kaikai You
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Patent number: 12225777Abstract: A display base plate includes: a substrate (101), a first electrode layer (102) formed on the substrate (101), and a first pixel definition layer (103) and a second pixel definition layer (104) formed on the first electrode layer (102); the first pixel definition layer (103) divides the substrate (101) into a plurality of pixel regions (105), each pixel region (105) includes a plurality of subpixel regions (1050) distributed along a first direction, and two adjacent subpixel regions (1050) are separated by the second pixel definition layer (104); in the first direction, surfaces of each pixel region (105) in contact with the first pixel definition layer (103) include a plurality of first curved surfaces (1061) and a plurality of second curved surfaces (1062), and the first curved surfaces (1061) and the second curved surfaces (1062) are protruded away from the pixel region (105) to which they belong.Type: GrantFiled: April 23, 2021Date of Patent: February 11, 2025Assignee: BOE Technology Group Co., Ltd.Inventors: Juanjuan You, Ying Cui, Yue Zhang
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Patent number: 12225779Abstract: A display substrate includes a base substrate, a thin film transistor array layer, a planarization layer, a first electrode and a pixel definition layer, the pixel definition layer defining a plurality of pixel openings, each pixel opening includes a first edge and a second edge adjacent to each other, the pixel definition layer includes a first pixel definition layer parallel to the first edge and a second pixel definition layer parallel to the second edge. A surface of the first pixel definition layer away from the base substrate is located at a level lower than a surface of the second pixel definition layer away from the base substrate, a groove parallel to the first edge is arranged in a surface of the planarization layer away from the base substrate, at least a part of the first pixel definition layer is arranged in the groove.Type: GrantFiled: April 15, 2021Date of Patent: February 11, 2025Assignee: BOE Technology Group Co., Ltd.Inventors: Linlin Wang, Ying Cui
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Publication number: 20250046376Abstract: The present disclosure provides a three-dimensional NAND memory device, comprising a memory array comprising blocks, each block includes first memory cells and second memory cells connected in series to a bit line, a word line driver, and a controller configured to control the word line driver to: performing a programming operation on a memory cell in the first memory cells, the memory cell is controlled by a selected word line of first word lines corresponding to the first memory cells, the first word lines comprising first unselected word lines adjacent to the selected word line, and the performing the programming operation comprises: applying a programming voltage signal to the selected word line to program the memory cell into a target state; applying a first pass voltage to the first unselected word lines; and applying a second pass voltage to second word lines corresponding to the second memory cells.Type: ApplicationFiled: September 21, 2023Publication date: February 6, 2025Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Ying CUI, SongMin JIANG, YaLi SONG, HongTao LIU
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Publication number: 20250039277Abstract: A system and method for joint dynamic interest request forwarding and dynamic cache placement and eviction and provided within the context of the Named Data Networking (NDN) architecture. The system and method employ a virtual control plane that operates on the user demand rate for data objects in the network, and an actual plane that handles Interest Packets and Data Packets. Distributed algorithms within the virtual plane achieve network load balancing through dynamic forwarding and caching, thereby maximizing the user demand rate that the NDN network can satisfy. A method of congestion control is also provided to achieve optimal network fairness using the VIP framework.Type: ApplicationFiled: September 26, 2024Publication date: January 30, 2025Inventors: Edmund Meng Yeh, Ying Cui, Ran Liu, Tracey Ho, Michael Burd, Derek Leong