Patents by Inventor Yingjun PI

Yingjun PI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11710646
    Abstract: A fan-out packaging method includes: prepare circuit patterns on one side or both sides of a substrate; install electronic parts on one side or both sides of the substrate; prepare packaging layers on both sides of the substrate; the packaging layers on both sides of the substrate package the substrate, the circuit patterns, and the electronic parts, the packaging layers being made of a thermal-plastic material; wherein the substrate is provided with a via hole; both sides of the substrate are communicated by means of the via hole; a part of the packaging layers penetrate through the via hole when the packaging layers are prepared on both sides of the substrate; and the packaging layers on both sides of the substrate are connected by means of the via hole.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: July 25, 2023
    Assignee: SHENZHEN XIUYI INVESTMENT DEVELOPMENT PARTNERSHIP (LIMITED PARTNERSHIP)
    Inventors: Chuan Hu, Yingqiang Yan, Yuejin Guo, Yingjun Pi, Junjun Liu, Edward Prack
  • Publication number: 20220051908
    Abstract: A fan-out packaging method includes: prepare circuit patterns on one side or both sides of a substrate; install electronic parts on one side or both sides of the substrate; prepare packaging layers on both sides of the substrate; the packaging layers on both sides of the substrate package the substrate, the circuit patterns, and the electronic parts, the packaging layers being made of a thermal-plastic material; wherein the substrate is provided with a via hole; both sides of the substrate are communicated by means of the via hole; a part of the packaging layers penetrate through the via hole when the packaging layers are prepared on both sides of the substrate; and the packaging layers on both sides of the substrate are connected by means of the via hole.
    Type: Application
    Filed: October 11, 2018
    Publication date: February 17, 2022
    Inventors: Chuan HU, Yingqiang YAN, Yuejin GUO, Yingjun PI, Junjun LIU, Edward PRACK
  • Publication number: 20210358883
    Abstract: A fan-out packaging method employing a combined process includes: manufacturing at least two layers of basic circuit patterns on a substrate; manufacturing a galvanic isolation layer on one of the two layers of basic circuit patterns; manufacturing a fine circuit pattern on the galvanic isolation layer; using a bonding layer to bond an electronic component to the galvanic isolation layer, and using a patch material to establish an electrical connection between the electronic component and the fine circuit pattern; and using a packaging layer to package the electronic component, wherein the fine circuit pattern has a width less than widths of the basic circuit patterns. In the present disclosure, multiple layers of circuits are manufactured before installation and packaging of electronic components, thereby reducing the number of times an insulation material is to be heated, and broadening the range of available types of insulation materials.
    Type: Application
    Filed: October 11, 2018
    Publication date: November 18, 2021
    Inventors: Chuan HU, Yingqiang YAN, Yuejin GUO, Yingjun PI, Junjun LIU