Patents by Inventor Yingkit Felix Tsui

Yingkit Felix Tsui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12259604
    Abstract: A method of fabricating an optical device comprises steps of forming a silicon-based optical component in a substrate; depositing an ILD layer on the substrate and the silicon-based optical component; forming a thermal tuning assembly comprising a first metallic material in the ILD layer and above the silicon-based optical component, wherein the thermal tuning assembly comprises a core above the silicon-based optical component, a plurality of grids spaced apart from the core, and a pair of neck portions connecting the grids to the core, wherein a width of a strip in each grid is greater than a width of the core; forming at least one conductive plug comprising the first metallic material penetrating the ILD layer and coupled to the silicon-based optical component; and forming a plurality of conductive lines comprising a second metallic material coupled to the thermal tuning assembly.
    Type: Grant
    Filed: March 28, 2023
    Date of Patent: March 25, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Wen-Shun Lo, Jing-Hwang Yang, Yingkit Felix Tsui
  • Patent number: 12259605
    Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a semiconductor substrate, a first dielectric layer, a second dielectric layer, a light modulator, a heater, and a first conductive contact. The first dielectric layer is disposed on the semiconductor substrate. The second dielectric layer is disposed on the first dielectric layer. The light modulator is disposed in the first dielectric layer. The heater is disposed in the second dielectric layer and above the light modulator. The first conductive contact is electrically connected to the light modulator. A top surface of the heater is coplanar with a top surface of the first conductive contact.
    Type: Grant
    Filed: March 16, 2022
    Date of Patent: March 25, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Wen-Shun Lo, Yingkit Felix Tsui
  • Publication number: 20250089397
    Abstract: A photodetector may include an absorption region that is formed to have an increasing depth (or thickness) in a direction that is approximately parallel to the direction of incident light that is to be projected onto the absorption region. The increasing depth of the absorption region in the direction that is approximately parallel with the direction of incident light enables the incident light to be more uniformly distributed along the length of the absorption region in the direction that is approximately parallel with the direction of incident light. This reduces the likelihood that a particular area of the absorption region reaches optical saturation, which may enable the photodetector to operate a sustained high photodetector sensitivity and/or a sustained high light detection performance, among other examples.
    Type: Application
    Filed: September 8, 2023
    Publication date: March 13, 2025
    Inventors: Hau-Yan LU, Chun-Yen PENG, YingKit Felix TSUI
  • Patent number: 12235490
    Abstract: A semiconductor structure includes a waveguide and an optical attenuator. The waveguide is disposed over an insulating layer and configured to guide light. The optical attenuator is connected to the waveguide. The optical attenuator has a first surface and a second surface opposite the first surface, and a cross-sectional width of the optical attenuator decreases from the first surface to the second surface.
    Type: Grant
    Filed: July 1, 2022
    Date of Patent: February 25, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Wei-Kang Liu, Lee-Shian Jeng, Chih-Tsung Shih, Hau-Yan Lu, Yingkit Felix Tsui
  • Publication number: 20250063743
    Abstract: Some implementations described herein provide techniques and apparatuses for an integrated circuit device including a trench capacitor structure that has a merged region. A material filling the merged region is different than a material that is included in electrode layers of the trench capacitor structure. Furthermore, the material filling the merged region includes a coefficient of thermal expansion and a modulus of elasticity that, in combination with the architecture of the trench capacitor structure, reduce thermally induced stresses and/or strains within the integrated circuit device relative to another integrated circuit device having a trench capacitor structure including a merged region and electrode layers of a same material.
    Type: Application
    Filed: August 15, 2023
    Publication date: February 20, 2025
    Inventors: Shu-Hui SU, Hsin-Li CHENG, YingKit Felix TSUI, Tuo-Hsin CHIEN, Jyun-Ying LIN, Shi-Min WU, Yu-Chi CHANG, Ting-Chen HSU
  • Publication number: 20250063845
    Abstract: A photonic device includes a substrate, a P-type doped component disposed over the substrate, an N-type doped component disposed over the substrate, an optical absorption layer disposed over the substrate, and a charging layer disposed over the substrate. The optical absorption layer is disposed between the P-type doped component and the N-type doped component. The optical absorption layer and the substrate have different material compositions. A charging layer is disposed between the P-type doped component and the N-type doped component. The charging layer has a first side surface that is substantially linear. The first side surface is in direct contact with the optical absorption layer.
    Type: Application
    Filed: November 17, 2023
    Publication date: February 20, 2025
    Inventors: Chun-Yen Peng, Hau-Yan Lu, YingKit Felix Tsui
  • Publication number: 20250044518
    Abstract: An edge coupler includes a substrate, a first cladding layer over the substrate, a core layer over the first cladding layer, and an ARC layer. The substrate has a first sidewall, the first cladding layer has a second sidewall aligned with the first sidewall, and the core layer has a third sidewall aligned with the second sidewall. The ARC layer lines the first sidewall, the second sidewall and the third sidewall. The ARC layer physically contacts and covers a surface of the substrate. A first height of the ARC layer varies along the surface of the substrate.
    Type: Application
    Filed: October 22, 2024
    Publication date: February 6, 2025
    Inventors: WEI-KANG LIU, CHIH-TSUNG SHIH, HAU-YAN LU, YINGKIT FELIX TSUI
  • Publication number: 20250048781
    Abstract: A modulator heater structure may include a plurality of regions having different thicknesses. For example, a heater ring of the modulator heater structure may have a first thickness. A heater pad of the modulator heater structure, that is configured to provide an electrical current to the heater ring, may have a second thickness that is greater than the first thickness. The lesser thickness of the heater ring of the modulator heater structure provides high electrical resistance in the heater ring, which enables the heater ring to quickly and efficiently generate heat. The greater thickness of the heater pad provides low electrical resistance in the second region, which enables the electrical current to be efficiently provided through the heater pad to the heater ring with reduced heat dissipation in the hear pad due to the lower electrical current dissipation in the heater pad.
    Type: Application
    Filed: August 4, 2023
    Publication date: February 6, 2025
    Inventors: Wen-Shun LO, Sheng Kai YEH, Jing-Hwang YANG, Chi-Yuan SHIH, Shih-Fen HUANG, YingKit Felix TSUI
  • Patent number: 12199139
    Abstract: Various embodiments of the present application are directed towards an integrated chip (IC). The IC comprises a trench capacitor overlying a substrate. The trench capacitor comprises a plurality of capacitor electrode structures, a plurality of warping reduction structures, and a plurality of capacitor dielectric structures. The plurality of capacitor electrode structures, the plurality of warping reduction structures, and the plurality of capacitor dielectric structures are alternatingly stacked and define a trench segment that extends vertically into the substrate. The plurality of capacitor electrode structures comprise a metal component and a nitrogen component. The plurality of warping reduction structures comprise the metal component, the nitrogen component, and an oxygen component.
    Type: Grant
    Filed: July 11, 2022
    Date of Patent: January 14, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ting-Chen Hsu, Hsin-Li Cheng, Jyun-Ying Lin, Yingkit Felix Tsui, Shu-Hui Su, Shi-Min Wu
  • Publication number: 20250017004
    Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate, a transistor, and a capacitor. The transistor includes a gate electrode disposed on the substrate. The capacitor is electrically connected to the transistor and includes a capacitor dielectric and a capacitor electrode. The capacitor dielectric and the capacitor electrode are stacked over the gate electrode of the transistor.
    Type: Application
    Filed: July 5, 2023
    Publication date: January 9, 2025
    Inventors: CHUN-YAO KO, LIANG-TAI KUO, SHIH-HSIEN CHEN, YINGKIT FELIX TSUI
  • Publication number: 20240418941
    Abstract: A method of forming a grating coupler includes: providing an initial design layout of the grating coupler, wherein the initial design layout includes: a taper section, comprising a pair of tapers; and a grating section coupled to the taper section, the grating section having an array of gratings, wherein the gratings includes gradually changing shapes, from a top-view perspective, from a first non-convex octagonal shape of a central grating, at a center of the grating section, of one of a second non-convex octagonal shape, a convex octagonal shape, and a quadrilateral shape, to an edge grating near an edge of the grating section. The method further includes: converting the initial design layout into a revised design layout through an optical proximity correction operation; and manufacturing the grating coupler using the revised design layout.
    Type: Application
    Filed: June 14, 2023
    Publication date: December 19, 2024
    Inventors: CHENG-TSE TANG, WEI-KANG LIU, HAU-YAN LU, YINGKIT FELIX TSUI
  • Publication number: 20240402521
    Abstract: An optical modulator structure in a photonic integrated circuit includes an L-shaped P-N junction at an optical mode of the optical modulator structure (e.g., an area of the optical modulator structure in which light is generated). The L-shaped P-N junction provides increased area of overlap of the P-N junction at the optical mode relative to another type of junction, such as a horizontal junction or I-shaped junction. The increased area of overlap may enable the optical modulator structure to achieve a greater modulation efficiency.
    Type: Application
    Filed: May 30, 2023
    Publication date: December 5, 2024
    Inventors: Wen-Shun LO, Ta-Wei CHOU, Chih-Tsung SHIH, Jing-Hwang YANG, Chi-Yuan SHIH, YingKit Felix TSUI, Shih-Fen HUANG
  • Patent number: 12156403
    Abstract: In some embodiments, the present disclosure relates to an integrated chip (IC), including a substrate, a floating gate electrode disposed over the substrate, a contact etch stop layer (CESL) structure disposed over the floating gate electrode, an insulating stack separating the floating gate electrode from the CESL structure, the insulating stack including a first resist protective layer disposed over the floating gate electrode, a second resist protective layer disposed over the first resist protective layer, and an insulating layer separating the first resist protective layer from the second resist protective layer.
    Type: Grant
    Filed: August 23, 2021
    Date of Patent: November 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Shun Lo, Tai-Yi Wu, Shih-Hsien Chen, Yingkit Felix Tsui
  • Patent number: 12153261
    Abstract: An edge coupler, a waveguide structure and a method for forming a waveguide structure are provided. The edge coupler includes a substrate, a first cladding layer, a core layer and a first anti-reflection coating layer. The first cladding layer has a second sidewall aligned with a first sidewall of the substrate. The core layer has a third sidewall aligned with the second sidewall. The anti-reflection coating layer lines the first sidewall, the second sidewall and the third sidewall. A thickness of the anti-reflection coating layer varies along the first sidewall, the second sidewall and the third sidewall.
    Type: Grant
    Filed: July 13, 2022
    Date of Patent: November 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Wei-Kang Liu, Chih-Tsung Shih, Hau-Yan Lu, Yingkit Felix Tsui
  • Publication number: 20240385372
    Abstract: An edge coupler has a wide end, a narrow end, and a tapering thickness. The narrow end is coupled to a waveguide in a photonic integrated circuit (PIC). The wide end is coupled to an optical transmitter or receiver. The edge coupler thickens by tapering downward into the buried oxide layer of a BOX substrate. An upper surface of the edge coupler may be planar. A pedestal may be formed in the oxide layer so that a laser diode mounted on the pedestal will be vertically aligned to the edge coupler. Alternatively, the pedestal may be formed in a substrate under the oxide layer so that the core of an optical fiber mounted on the pedestal will be vertically aligned to the edge coupler. The pedestal may be in a cavity that facilitates horizontal alignment between the laser diode, optical fiber, or other such device and the edge coupler.
    Type: Application
    Filed: May 19, 2023
    Publication date: November 21, 2024
    Inventors: Hau-Yan Lu, Wei-Kang Liu, Yingkit Felix Tsui
  • Publication number: 20240385375
    Abstract: In some embodiments, the present disclosure relates to a device having a first waveguide and a second waveguide arranged over a substrate. The first waveguide has a first input terminal and a first output terminal, wherein the first input terminal is configured to receive light. The second waveguide is arranged laterally beside the first waveguide and has a second input terminal and a second output terminal. The second input terminal of the second waveguide is configured to receive light. The first waveguide further includes a first portion that has a different structure than surrounding portions of the first waveguide. The second waveguide further includes a second portion that has a different structure than surrounding portions of the second waveguide. The first waveguide is spaced apart at a maximum distance from the second waveguide at the first portion and the second portion.
    Type: Application
    Filed: July 26, 2024
    Publication date: November 21, 2024
    Inventors: Min-Hsiang Hsu, Cheng-Tse Tang, Hau-Yan Lu, Yingkit Felix Tsui
  • Publication number: 20240377659
    Abstract: The present disclosure provides an optical modulating structure. The optical modulating structure includes a lower member extending along an insulating layer, a first protrusion over the lower member, and a second protrusion over the lower member and separated from the first protrusion. A first mask layer is formed over the optical modulating structure, wherein the first mask layer covers the second protrusion and a first portion of the lower member between the first protrusion and the second protrusion. A first doping region is formed in an exposed portion of the lower member and at least a portion of an exposed sidewall of the first protrusion. A dielectric layer is formed between the first protrusion and the second protrusion. A method for manufacturing the optical modulating structure is also provided.
    Type: Application
    Filed: May 10, 2023
    Publication date: November 14, 2024
    Inventors: WEN-SHUN LO, YINGKIT FELIX TSUI, JING-HWANG YANG
  • Publication number: 20240379808
    Abstract: A semiconductor device includes a substrate having a P-well region, an N-well region disposed on either side of and abutting the P-well region, and a deep N-well region disposed beneath and abutting both the P-well region and at least part of the N-well region on either side of the P-well region. The semiconductor device further includes a first conductive layer formed over a cathode region of the P-well region, where a Schottky barrier is formed at a junction of the first conductive layer and the P-well region. The semiconductor device further includes a second conductive layer formed over anode regions of the P-well region, where the anode regions are disposed on either side of the cathode region.
    Type: Application
    Filed: July 22, 2024
    Publication date: November 14, 2024
    Inventors: Wen-Shun Lo, Yu-Chi Chang, Yingkit Felix Tsui
  • Patent number: 12140796
    Abstract: In some embodiments, the present disclosure relates to a device having a first waveguide and a second waveguide arranged over a substrate. The first waveguide has a first input terminal and a first output terminal, wherein the first input terminal is configured to receive light. The second waveguide is arranged laterally beside the first waveguide and has a second input terminal and a second output terminal. The second input terminal of the second waveguide is configured to receive light. The first waveguide further includes a first portion that has a different structure than surrounding portions of the first waveguide. The second waveguide further includes a second portion that has a different structure than surrounding portions of the second waveguide. The first waveguide is spaced apart at a maximum distance from the second waveguide at the first portion and the second portion.
    Type: Grant
    Filed: August 3, 2021
    Date of Patent: November 12, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Min-Hsiang Hsu, Cheng-Tse Tang, Hau-Yan Lu, Yingkit Felix Tsui
  • Publication number: 20240369764
    Abstract: A semiconductor structure includes a grating coupler structure, a circuit component separated from the grating coupler structure, an inter level dielectric layer, a capping layer over the inter level dielectric layer, and a passivation layer over the capping layer. The inter level dielectric layer has a first refractive index, the capping layer has second refractive index, and the passivation layer has a third refractive index. The second refractive index is greater than the first refractive index, and is greater than the third refractive index.
    Type: Application
    Filed: July 21, 2024
    Publication date: November 7, 2024
    Inventors: CHIH-TSUNG SHIH, WEI-KANG LIU, SUI-YING HSU, JING-HWANG YANG, YINGKIT FELIX TSUI