Abstract: There is provided a gate driving circuit comprising N first shift registers arranged alternately with N second shift registers. An input signal terminal of an n-th stage of first shift register is coupled to an output signal terminal of an (n?i)-th stage of first shift register, and a reset signal terminal of the n-th stage of first shift register is coupled to an output signal terminal of an (n+j)-th stage of first shift register. Input signal terminal and reset signal terminal of n-th stage of second shift register are coupled to output signal terminals of (n?i)-th and (n+j)-th stages of second shift registers respectively. K=6, i=3, and j=4. Reset signal terminals of (N?j+1)-th to N-th stages of first shift registers and reset signal terminals of (N?j+1)-th to N-th stages of second shift registers are configured to receive a total reset signal.

Abstract: An array substrate and a touch display device are provided. In the array substrate, a first control unit and a second control unit are arranged opposite to each other in a first direction. A plurality of touch sensor blocks includes a first group of electrode blocks and a second group of electrode blocks arranged in the first direction, and a plurality of touch signal lines includes a first group of touch signal lines and a second group of touch signal lines arranged in the first direction. The touch signal lines in the first group of touch signal lines are coupled to the touch sensor blocks in the first group of electrode blocks respectively; and the touch signal lines in the second group of touch signal lines are coupled to the touch sensor blocks in the second group of electrode blocks respectively.

Abstract: Provided are an array substrate and a manufacturing method thereof, and a display device. The array substrate comprises a plurality of data lines and sub-pixels. At least one sub-pixel comprises: a first insulating layer; a gate; an active layer located on one side of the first insulating layer away from the gate; a pixel electrode; a first electrode located connected to the active layer and in contact with the pixel electrode; a second electrode connected to the active layer and a data line; a second insulating layer having a first opening, wherein the orthographic projection of the first opening partially overlaps with the orthographic projections of the pixel electrode and the first electrode; a connection electrode in contact with the pixel electrode and the first electrode through the first opening; and a common electrode located on one side of the second insulating layer away from the pixel electrode.

Abstract: According to the embodiments of the present disclosure, there is provided gate driving circuit comprising 2N stages of shift registers, the 2N stages of shift registers comprising N first shift registers arranged alternately with N second shift registers, wherein the N first shift registers are cascaded-coupled as N stages of first shift registers, and are configured to generate N first output signals under control of K first clock signals; and wherein the N second shift registers are cascaded-coupled as N stages of second shift registers, and are configured to generate N second output signals under a control of K second clock signals, wherein K and N are both integers greater than 1, and K?N.

Abstract: An array substrate, a display panel, and an electronic device are provided. The array substrate includes: a base substrate; a first electrode arranged on the base substrate; a gate line arranged on the base substrate, wherein the gate line is electrically insulated from the first electrode; a second electrode arranged on a side of the gate line away from the base substrate, wherein at least one first sub-pixel unit provided on the base substrate includes: a first connection portion arranged in a same layer as the second electrode and a second connection portion arranged in a same layer as the gate line, wherein the second connection portion is electrically connected to the first electrode, and an orthographic projection of the second connection portion on the base substrate at least partially overlaps an orthographic projection of the first connection portion on the base substrate.

Abstract: An array substrate and a manufacturing method thereof, a motherboard and a display device are disclosed. The array substrate has a display region and a non-display region, and includes a base substrate, and a plurality of signal lines and at least one transfer electrode that are on the base substrate. The plurality of signal lines extend from the display region to the non-display region along a first direction, at least one of the plurality of signal lines includes a first trace in the display region and a second trace in the non-display region, the second trace includes at least two sub-traces disconnected from each other, a sub-trace, close to the display region, of the at least two sub-traces of the second trace is directly connected with the first trace, and every two adjacent sub-traces of the second trace are electrically connected with each other.

Abstract: The present disclosure provides a display substrate and a display device. The display substrate includes: a gate driving circuitry arranged at a peripheral region of the display substrate; n clock signal leads coupled to the gate driving circuitry, each clock signal lead extending in a first direction; and n clock signal lines arranged sequentially in the first direction, each clock signal line extending in a second direction intersecting the first direction, where n is a positive integer greater than 1. The clock signal leads have a same length in the first direction, each clock signal lead extends from a first clock signal line to an nth clock signal line, and each clock signal lead is coupled to a corresponding clock signal line at a position where the clock signal lead intersects the clock signal line.

Abstract: The present disclosure relates to the field of display technology, and in particular, to an array substrate and a display apparatus. The array substrate has a display area and a peripheral wiring area provided at at least one side of the display area. The display area includes a thin film transistor and a common electrode formed on the base substrate; the peripheral wiring area includes a first lead, a gate signal line and a common signal line formed on the base substrate; the first lead and the gate electrode of the thin film transistor are arranged in an identical layer and are electrically connected; the gate signal line is located on a side of the first lead away from the base substrate, and is electrically connected to the first lead through a first transition structure.

Abstract: An array substrate includes a base substrate, pixel electrodes and common electrodes, first scan lines, second scan lines and data lines. The pixel electrode has first electrode strips disposed at intervals in a row direction. The common electrodes and the pixel electrodes are disposed on the same layer, and the common electrodes have second electrode strips disposed at intervals. The second electrode strips and the first electrode strips are alternatively arranged. The first scan line is located between two adjacent rows of pixel electrodes. The second scan line is located between two adjacent columns of pixel electrodes and is electrically connected to the first scan line, and the second scan line has a scan signal input terminal. The data line has a data signal input terminal. An orthographic projection of the data line on the base substrate intersects with a central region of the pixel electrode on the base substrate.

Abstract: A display device and a method for bonding the display device are provided. The display device includes a display panel and a plurality of chip on films. The plurality of chip on films are arranged along a first edge of the display panel, and are divided into a plurality of groups of chip on films, and each group of chip on films includes at least two chip on films, and is bonded to the display panel through a same anisotropic conductive film.

Abstract: An array substrate, a light control panel, and a display device are disclosed. The array substrate includes a data line layer, a base substrate, a first electrode layer, and a second electrode layer. The first electrode layer includes gate lines, each gate line integrally extends along a first direction, and includes first broken line structures directly connected in sequence in the first direction; the data line layer includes data lines, each data line integrally extends along a second direction; the gate lines and the data lines cross each other to define light control pixel units; the second electrode layer includes common electrodes, each common electrode is provided in at least one light control pixel unit; and at least one gate line at least partially overlaps with an orthographic projection of at least one common electrode on the first electrode layer.

Abstract: A gate driving circuit, a method for driving the gate driving circuit, and a display panel. The gate driving circuit includes N-stages of cascaded shift registers divided into at least one group of K-stages in which a clock signal terminal of a k-th stage of shift register is connected to receive a k-th clock signal, where N, k and K are positive integers, and 1?k?K?N; and an input signal terminal of a n-th stage of shift register is connected to an output signal terminal of a (n?i)-th stage of shift register, and reset signal terminals of the n-th and (n+1)-th stages of shift registers are connected to an output signal terminal of a (n+j)-th stage of shift register, wherein the n is one of an odd number and an even number, where i and j are positive integers, 1<n<N, (K?2)/2?i?K/2, and K/2<j?K?2.

Abstract: According to the embodiments of the present disclosure, there is provided gate driving circuit comprising 2N stages of shift registers, the 2N stages of shift registers comprising N first shift registers arranged alternately with N second shift registers, wherein the N first shift registers are cascaded-coupled as N stages of first shift registers, and are configured to generate N first output signals under control of K first clock signals; and wherein the N second shift registers are cascaded-coupled as N stages of second shift registers, and are configured to generate N second output signals under a control of K second clock signals, wherein K and N are both integers greater than 1, and K?N.

Abstract: A display substrate includes: a base, a plurality of pixel units arranged in columns in a first direction and in rows in a second direction, a plurality of data lines and first gate lines extending in the first direction, a plurality of second gate lines extending in the second direction, and at least one gate driver circuit connected to the first gate lines and located at a side of the display substrate parallel to the second direction. One pixel unit includes a TFT. The TFT is connected to one data line. In a column of pixel units, TFTs of any two adjacent pixel units are respectively located at first and second sides of a respective data line. Each second gate line is connected to a row of pixel units and at least one of the first gate lines. First gate lines connecting different second gate lines are different.

Abstract: A driving method of display panel, a display panel and a display device are disclosed. The driving method includes: in a single-frame display time, sequentially applying signals to a plurality of first sub-pixels connected to first data lines in a scanning direction so that: a signal polarity applied to each of a plurality of first white sub-pixels connected to first data lines is opposite to a signal polarity applied to a first sub-pixel which is located at an upstream of the first white sub-pixel along the scanning direction and is adjacent to the first white sub-pixel, and a signal polarity applied to each of a plurality of first colored sub-pixels is identical with a signal polarity applied to a first sub-pixel which is located at an upstream of the first colored sub-pixel along the scanning direction and is adjacent to the first colored sub-pixel.

Abstract: A supplement resetting module for a gate driver circuit, including a pull-up control unit, a pull-down control unit, a clock signal input end, a predetermined level input end, a first control signal input end, a second control signal input end and a signal output end. A control end of the pull-up control unit is connected to the clock signal input end, an output end of the pull-up control unit is connected to the signal output end, a first control end of the pull-down control unit is connected to the first control signal input end, a second control end of the pull-down control unit is connected to the second control signal input end, an input end of the pull-down control unit is connected to the predetermined level input end, and an output end of the pull-down control unit is connected to the signal output end.

Abstract: A shift register unit, a driving method, and a gate driving circuit are disclosed. The shift register unit includes an input reset sub-circuit, which is connected to a first scan control terminal, a second scan control terminal, a first scan level terminal, a second scan level terminal and a pull-up node, respectively, and configured to control the pull-up node to connect with the first scan level terminal or the second scan level terminal under the control of a first scan control signal fed through the first scan control terminal and a second scan control signal fed through the second scan control terminal; a gate driving signal output sub-circuit; and a gate driving signal reset sub-circuit.

Abstract: A supplement resetting module for a gate driver circuit, including a pull-up control unit, a pull-down control unit, a clock signal input end, a predetermined level input end, a first control signal input end, a second control signal input end and a signal output end. A control end of the pull-up control unit is connected to the clock signal input end, an output end of the pull-up control unit is connected to the signal output end, a first control end of the pull-down control unit is connected to the first control signal input end, a second control end of the pull-down control unit is connected to the second control signal input end, an input end of the pull-down control unit is connected to the predetermined level input end, and an output end of the pull-down control unit is connected to the signal output end.

Abstract: A driving method of display panel, a display panel and a display device are disclosed. The driving method includes: in a single-frame display time, sequentially applying signals to a plurality of first sub-pixels connected to first data lines in a scanning direction so that: a signal polarity applied to each of a plurality of first white sub-pixels connected to the first data lines is opposite to a signal polarity applied to a first sub-pixel which is located at an upstream of the first white sub-pixel along the scanning direction and is adjacent to the first white sub-pixel, and a signal polarity applied to each of a plurality of first colored sub-pixels is identical with a signal polarity applied to a first sub-pixel which is located at an upstream of the first colored sub-pixel along the scanning direction and is adjacent to the first colored sub-pixel.

Abstract: Embodiments of the disclosure disclose a gate driving circuit, a driving method, and a display device. In the gate driving circuit, the input module transmits the input signal of the input signal terminal to the first node. The reset module resets the first node and the output terminal of the gate driving circuit. The pull-down module pulls down the signal of the first node and the signal of the output terminal of the gate driving circuit to low level signals. The pull-down control module generates a voltage signal of the second node based on the signal of the noise-canceling signal terminal, and controls the pull-down module to pull down a high level noise signal at the first node to a low level signal using the voltage signal. The pull-up module pulls up the signal of the output terminal of the gate driving circuit to a high level signal.