Abstract: A display substrate, including: a base substrate; a plurality of data lines on the base substrate; a first insulating layer on a side of the plurality of data lines away from the base substrate; a plurality of gate lines on a side of the first insulating layer away from the plurality of data lines, where extension directions of the gate and data lines are intersected; a second insulating layer on a side of the plurality of gate lines away from the first insulating layer; and a first electrode on a side of the second insulating layer away from the plurality of gate lines, where at least a portion of an orthographic projection of the first electrode on the base substrate is within an region surrounded by orthographic projections of two adjacent data lines on the base substrate and orthographic projections of two adjacent gate lines on the base substrate.

Abstract: A display panel and a display device are disclosed. The display panel includes a gate driving circuit, a plurality of clock signal lines, a timing controller and a plurality of anti-cross-row circuits; the timing controller is configured to provide a first clock signal; the plurality of anti-cross-row circuits are connected with the timing controller and the plurality of clock signal lines, and are configured to adjust the first clock signal provided by the timing controller to a second clock signal, and output the second clock signal to the plurality of clock signal lines, and a falling duration of a falling edge of the second clock signal is less than a falling duration of a falling edge of the first clock signal; and each of the plurality of anti-cross-row circuits comprises at least one resistor and at least one inductor.

Abstract: A driving circuit, a display device, and a driving method are disclosed. The driving circuit includes a level conversion unit and a gate electrode driving unit; and the gate electrode driving unit is configured to sequentially shift and output a plurality of first gate scan signals by a first portion of the 2n gate signal output terminals in response to a first portion of the plurality of first output signals received at a first moment by a first portion of the plurality of second clock signal input terminals, and sequentially output a plurality of second gate scan signals by a second portion of the 2n gate signal output terminals in response to a second portion of the plurality of first output signals received at a second moment by a second portion of the plurality of second clock signal input terminals.

Abstract: A driving method for a display panel and a display apparatus. The driving method includes: obtaining original display data of a current display frame; and when it is determined to adopt a first driving mode, loading first gate scanning signals (GA1_1-GA12_1) to gate lines (GA, GA1-GA12) in the display panel, and loading a data voltage to data lines (DA, DA1-DA7) in the display panel according to target display data obtained by removing a part of data from the original display data, so as to charge each sub-pixel in the display panel with the data voltage.

Abstract: A driving method for a display panel and a display apparatus. The driving method includes: acquiring display data of a to-be-displayed image in a current display frame (S100); and loading a data voltage on a data line in the display panel according to the display data, such that each sub-pixel in the display panel is charged with the corresponding data voltage (S200).

Abstract: Provided are a display apparatus and a method for driving display apparatus. The display apparatus includes a display substrate; the display substrate includes: gate drive circuit, connected with gate lines disposed in the display area; a plurality of clock signal lines; and a bonding pad; a first circuit board; and a second circuit board; the first circuit board and the second circuit board are independent of each other; the first circuit board is disposed at a side, facing away from the display area, of the second circuit board; the first circuit board and the second circuit board are electrically connected with the bonding pad; the first circuit board is electrically connected with the gate drive circuit via the plurality of clock signal lines; and in an extension direction of the gate line, a width of the first circuit board is smaller than a width of the second circuit board.

Abstract: An array substrate includes a gate drive circuit including shift register units in cascade. The driving method includes: in a first driving mode, loading a first clock signal with an active level and an inactive level alternating periodically to a cascade clock signal terminal of a shift register unit, and loading a second clock signal with an active level and an inactive level alternating periodically to any one of K drive clock signal terminals of the shift register unit; and in a second driving mode, loading the first clock signal to the cascade clock signal terminal, and loading a third clock signal with an active level appearing within a target time period to a target drive clock signal terminal among the K drive clock signal terminals so that a target drive output terminal corresponding to the target drive clock signal terminal outputs a gate turn-on signal.

Abstract: A display driving method, a display driving device and a display device are provided. The display driving method includes: when displaying an odd-numbered frame, providing first parity row data of the odd-numbered frame to a display array, to enable a third parity row of the display array to be displayed based on real data of the first parity row data and enable a fourth parity row of the display array to be displayed based on interpolation data of the first parity row data; and when displaying an even-numbered frame, providing second parity row data of the even-numbered frame to the display array, to enable the fourth parity row of the display array to be displayed based on real data of the second parity row data and enable the third parity row of the display array to be displayed based on interpolation data of the second parity row data.

Abstract: Provided are a display apparatus and a method for driving display apparatus. The display apparatus includes a display substrate; the display substrate includes: gate drive circuit, connected with gate lines disposed in the display area; a plurality of clock signal lines; and a bonding pad; a first circuit board; and a second circuit board; the first circuit board and the second circuit board are independent of each other; the first circuit board is disposed at a side, facing away from the display area, of the second circuit board; the first circuit board and the second circuit board are electrically connected with the bonding pad; the first circuit board is electrically connected with the gate drive circuit via the plurality of clock signal lines; and in an extension direction of the gate line, a width of the first circuit board is smaller than a width of the second circuit board.

Abstract: A gate driving circuit is provided, including N-stages of cascaded shift registers divided into at least one group of K-stages in which a clock signal terminal of a k-th stage of shift register is connected to receive a k-th clock signal, where 1?k?K?N; and an input signal terminal of a n-th stage is connected to an output signal terminal of a (n?i)-th stage, and reset signal terminals of the n-th and (n+1)-th stages are connected to an output signal terminal of a (n+j)-th stage, where 1<n<N, (K?2)/2?i?K/2, and K/2<j?K?2. K=12, the input signal terminal of the n-th stage is connected to an output signal terminal of a (n?6)-th stage, and the reset signal terminals of the n-th stage and the (n+1)-th stage are connected to an output signal terminal of a (n+8)-th stage or a (n+10) stage.

Abstract: An array substrate, a display panel, and an electronic device are provided. The array substrate includes: a base substrate; a first electrode arranged on the base substrate; a gate line arranged on the base substrate, wherein the gate line is electrically insulated from the first electrode; a second electrode arranged on a side of the gate line away from the base substrate, wherein at least one first sub-pixel unit provided on the base substrate includes: a first connection portion arranged in a same layer as the second electrode and a second connection portion arranged in a same layer as the gate line, wherein the second connection portion is electrically connected to the first electrode, and an orthographic projection of the second connection portion on the base substrate at least partially overlaps an orthographic projection of the first connection portion on the base substrate.

Abstract: A display panel and a display device are disclosed. The display panel includes a gate driving circuit, a plurality of clock signal lines, a timing controller and a plurality of anti-cross-row circuits; the timing controller is configured to provide a first clock signal; the plurality of anti-cross-row circuits are connected with the timing controller and the plurality of clock signal lines, and are configured to adjust the first clock signal provided by the timing controller to a second clock signal, and output the second clock signal to the plurality of clock signal lines, and a falling duration of a falling edge of the second clock signal is less than a falling duration of a falling edge of the first clock signal; and each of the plurality of anti-cross-row circuits comprises at least one resistor and at least one inductor.

Abstract: A display panel, a driving method for the display panel and a display device. The display panel includes a gate driving circuit, the gate driving circuit includes shift registers of a plurality of stages arranged in sequence, the shift registers of the plurality of stages arranged in sequence are combined into N groups of gate driving sub-circuits, and shift registers in the N groups of gate driving sub-circuits are cascaded, respectively; an m-th group of gate driving sub-circuits in the N groups of gate driving sub-circuits comprises a shift register of an m-th stage and a shift register of an (m+L*N)th stage that are cascaded, where m is an integer that is greater than or equal to 1 and less than or equal to N, L is an integer that is greater than or equal to 1, N is an even number that is greater than or equal to 2.

Abstract: The present application relates to the technical field of display. Disclosed are an array substrate and a display panel. The array substrate comprises: a substrate, and scanning lines, scanning signal lines, data line pairs, thin film transistors and pixel electrodes, which are arranged on the substrate, wherein the substrate has a display area, and the display area comprises sub-pixel areas, which are distributed in an array; two adjacent scanning lines form a scanning line group, the scanning signal lines extend in a column direction, and one scanning signal line is electrically connected to only two scanning lines in one scanning line group; each data line pair comprises two data lines, sub-pixel columns are provided in one-to-one correspondence with the data line pairs, and the two data lines in each data line pair pass through corresponding sub-pixel areas in the column direction; and in a row direction, a light-shielding strip is provided between every two adjacent sub-pixel areas.

Abstract: A display driving method, a display driving device and a display device are provided. The display driving method includes: when displaying an odd-numbered frame, providing first parity row data of the odd-numbered frame to a display array, to enable a third parity row of the display array to be displayed based on real data of the first parity row data and enable a fourth parity row of the display array to be displayed based on interpolation data of the first parity row data; and when displaying an even-numbered frame, providing second parity row data of the even-numbered frame to the display array, to enable the fourth parity row of the display array to be displayed based on real data of the second parity row data and enable the third parity row of the display array to be displayed based on interpolation data of the second parity row data.

Abstract: Provided are an array substrate and a manufacturing method thereof, and a display device. The array substrate includes a plurality of data lines and sub-pixels. At least one sub-pixel includes: a first insulating layer; a gate; an active layer located on one side of the first insulating layer away from the gate; a pixel electrode; a first electrode located connected to the active layer and in contact with the pixel electrode; a second electrode connected to the active layer and a data line; a second insulating layer having a first opening, wherein the orthographic projection of the first opening partially overlaps with the orthographic projections of the pixel electrode and the first electrode; a connection electrode in contact with the pixel electrode and the first electrode through the first opening; and a common electrode located on one side of the second insulating layer away from the pixel electrode.

Abstract: An array substrate and a manufacturing method thereof, a motherboard and a display device are disclosed. The array substrate has a display region and a non-display region, and includes a base substrate, and a plurality of signal lines and at least one transfer electrode that are on the base substrate. The plurality of signal lines extend from the display region to the non-display region along a first direction, at least one of the plurality of signal lines includes a first trace in the display region and a second trace in the non-display region, the second trace includes at least two sub-traces disconnected from each other, a sub-trace, close to the display region, of the at least two sub-traces of the second trace is directly connected with the first trace, and every two adjacent sub-traces of the second trace are electrically connected with each other.

Abstract: The dual gate array substrate of the present disclosure includes a plurality of groups of dual gate lines, a plurality of data lines, a plurality of pixel pairs and a plurality of common electrode lines, each common electrode line is arranged between two pixel units in a same pixel pair and is connected to common electrodes of the two pixel units through two first vias; a layer where the common electrode line is located and a layer where a source/drain electrode of a thin film transistor is located are different layers and insulated from each other; the two first vias are on both sides of the data line.

Abstract: Provided are an array substrate and a manufacturing method thereof, and a display device. The array substrate comprises a plurality of data lines and sub-pixels. At least one sub-pixel comprises: a first insulating layer; a gate; an active layer located on one side of the first insulating layer away from the gate; a pixel electrode; a first electrode located connected to the active layer and in contact with the pixel electrode; a second electrode connected to the active layer and a data line; a second insulating layer having a first opening, wherein the orthographic projection of the first opening partially overlaps with the orthographic projections of the pixel electrode and the first electrode; a connection electrode in contact with the pixel electrode and the first electrode through the first opening; and a common electrode located on one side of the second insulating layer away from the pixel electrode.

Abstract: An array substrate and a touch display device are provided. In the array substrate, a first control unit and a second control unit are arranged opposite to each other in a first direction. A plurality of touch sensor blocks includes a first group of electrode blocks and a second group of electrode blocks arranged in the first direction, and a plurality of touch signal lines includes a first group of touch signal lines and a second group of touch signal lines arranged in the first direction. The touch signal lines in the first group of touch signal lines are coupled to the touch sensor blocks in the first group of electrode blocks respectively; and the touch signal lines in the second group of touch signal lines are coupled to the touch sensor blocks in the second group of electrode blocks respectively.