Patents by Inventor Ying-Ming Wang
Ying-Ming Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11957064Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a spacer adjacent to the MTJ, a liner adjacent to the spacer, and a first metal interconnection on the MTJ. Preferably, the first metal interconnection includes protrusions adjacent to two sides of the MTJ and a bottom surface of the protrusions contact the liner directly.Type: GrantFiled: October 18, 2022Date of Patent: April 9, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Hui-Lin Wang, Chen-Yi Weng, Yi-Wei Tseng, Chin-Yang Hsieh, Jing-Yin Jhang, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, I-Ming Tseng, Yu-Ping Wang
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Publication number: 20240081157Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on one side of the of the MTJ, a second spacer on another side of the MTJ, a first metal interconnection on the MTJ, and a liner adjacent to the first spacer, the second spacer, and the first metal interconnection. Preferably, each of a top surface of the MTJ and a bottom surface of the first metal interconnection includes a planar surface and two sidewalls of the first metal interconnection are aligned with two sidewalls of the MTJ.Type: ApplicationFiled: November 6, 2023Publication date: March 7, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Hui-Lin Wang, Chen-Yi Weng, Yi-Wei Tseng, Chin-Yang Hsieh, Jing-Yin Jhang, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, I-Ming Tseng, Yu-Ping Wang
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Publication number: 20240074328Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on one side of the of the MTJ, a second spacer on another side of the MTJ, a first metal interconnection on the MTJ, and a liner adjacent to the first spacer, the second spacer, and the first metal interconnection. Preferably, each of a top surface of the MTJ and a bottom surface of the first metal interconnection includes a planar surface and two sidewalls of the first metal interconnection are aligned with two sidewalls of the MTJ.Type: ApplicationFiled: November 6, 2023Publication date: February 29, 2024Applicant: United Microelectronics Corp.Inventors: Hui-Lin Wang, Chen-Yi Weng, Yi-Wei Tseng, Chin-Yang Hsieh, Jing-Yin Jhang, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, I-Ming Tseng, Yu-Ping Wang
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Patent number: 11917551Abstract: Embodiments of the present invention are drawn to methods and electronic devices capable of performing coordinate spatial reuse for wirelessly transmitting data on a channel in coordination with another wireless AP operating an overlapping BSS using the same wireless channel. The device can perform RSSI measurements and generate Per-RU RSSI reports including the RSSI measurements information for transmission to another wireless AP. The RSSI measurement can be performed by the device based on power levels detected when receiving TB PPDUs transmitted by wireless STAs responsive to trigger frames, for example. Based on the Per-RU RSSI report, a wireless AP can be configured to transmit data to an associated wireless STA without causing significant interference when another AP of the overlapping BSS is also transmitting, and can schedule frames for transmission from associated wireless STAs accordingly.Type: GrantFiled: March 30, 2021Date of Patent: February 27, 2024Assignee: MEDIATEK SINGAPORE PTE. LTD.Inventors: Yongho Seok, Gary A. Anwyl, Jianhan Liu, Kai Ying Lu, James Chih-Shi Yee, Thomas Edward Pare, Jr., James June-Ming Wang
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Publication number: 20220367671Abstract: A semiconductor device and a method of forming the same are provided. A method includes forming a fin extending from a substrate. A sacrificial gate electrode layer is formed along a sidewall and a top surface of the fin. A patterning process is performed on the sacrificial gate electrode layer to form a sacrificial gate electrode. A reshaping process is performed on the sacrificial gate electrode to form a reshaped sacrificial gate electrode. The reshaped sacrificial gate electrode includes a first portion along the top surface of the fin and a second portion along the sidewall of the fin. A width of the first portion decreases as the first portion extends from a top surface of the first portion toward the top surface of the fin. A width of the second portion decreases as the second portion extends from the top surface of the fin toward the substrate.Type: ApplicationFiled: July 28, 2022Publication date: November 17, 2022Inventors: Ru-Shang Hsiao, Ying Ming Wang, Ying Hsin Lu
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Patent number: 11450758Abstract: A semiconductor device and a method of forming the same are provided. A method includes forming a fin extending from a substrate. A sacrificial gate electrode layer is formed along a sidewall and a top surface of the fin. A patterning process is performed on the sacrificial gate electrode layer to form a sacrificial gate electrode. A reshaping process is performed on the sacrificial gate electrode to form a reshaped sacrificial gate electrode. The reshaped sacrificial gate electrode includes a first portion along the top surface of the fin and a second portion along the sidewall of the fin. A width of the first portion decreases as the first portion extends from a top surface of the first portion toward the top surface of the fin. A width of the second portion decreases as the second portion extends from the top surface of the fin toward the substrate.Type: GrantFiled: June 12, 2020Date of Patent: September 20, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ru-Shang Hsiao, Ying Ming Wang, Ying Hsin Lu
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Publication number: 20210391441Abstract: A semiconductor device and a method of forming the same are provided. A method includes forming a fin extending from a substrate. A sacrificial gate electrode layer is formed along a sidewall and a top surface of the fin. A patterning process is performed on the sacrificial gate electrode layer to form a sacrificial gate electrode. A reshaping process is performed on the sacrificial gate electrode to form a reshaped sacrificial gate electrode. The reshaped sacrificial gate electrode includes a first portion along the top surface of the fin and a second portion along the sidewall of the fin. A width of the first portion decreases as the first portion extends from a top surface of the first portion toward the top surface of the fin. A width of the second portion decreases as the second portion extends from the top surface of the fin toward the substrate.Type: ApplicationFiled: June 12, 2020Publication date: December 16, 2021Inventors: Ru-Shang Hsiao, Ying Ming Wang, Ying Hsin Lu
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Patent number: 10930783Abstract: Semiconductor devices, FinFET devices with optimized strained-source-drain recess profiles and methods of forming the same are provided. One of the semiconductor devices includes a substrate, a gate stack over the substrate and a strained layer in a recess of the substrate and aside the gate stack. Besides, a ratio of a depth at the greatest width of the recess to a width of the gate stack ranges from about 0.5 to 0.7.Type: GrantFiled: November 7, 2018Date of Patent: February 23, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ying Ting Hsia, Kun Yu Lin, Ying Ming Wang, Li-Te Hsu
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Patent number: 10852469Abstract: A display panel includes an inner frame, a backlight module, an outer frame, and a light modulation module. The inner frame includes an inner surface forming a light guide plate accommodating area in a surrounding manner. The backlight module includes a light guide plate and a first optical film. The light guide plate is disposed in the light guide plate accommodating area, and the first optical film is carried on the inner frame. The outer frame includes a bottom portion and a sidewall portion that are connected to each other, in which the bottom portion and the sidewall portion form a receiving area, and the inner frame and the backlight module are located in the receiving area. The light modulation module is disposed on the first optical film. An orthogonal projection of the light modulation module in a vertical direction completely falls within the light guide plate accommodating area.Type: GrantFiled: February 25, 2019Date of Patent: December 1, 2020Assignee: AU OPTRONICS CORPORATIONInventor: Ying-Ming Wang
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Publication number: 20190278017Abstract: A display panel includes an inner frame, a backlight module, an outer frame, and a light modulation module. The inner frame includes an inner surface forming a light guide plate accommodating area in a surrounding manner. The backlight module includes a light guide plate and a first optical film. The light guide plate is disposed in the light guide plate accommodating area, and the first optical film is carried on the inner frame. The outer frame includes a bottom portion and a sidewall portion that are connected to each other, in which the bottom portion and the sidewall portion form a receiving area, and the inner frame and the backlight module are located in the receiving area. The light modulation module is disposed on the first optical film. An orthogonal projection of the light modulation module in a vertical direction completely falls within the light guide plate accommodating area.Type: ApplicationFiled: February 25, 2019Publication date: September 12, 2019Inventor: Ying-Ming Wang
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Publication number: 20190081176Abstract: Semiconductor devices, FinFET devices with optimized strained-source-drain recess profiles and methods of forming the same are provided. One of the semiconductor devices includes a substrate, a gate stack over the substrate and a strained layer in a recess of the substrate and aside the gate stack. Besides, a ratio of a depth at the greatest width of the recess to a width of the gate stack ranges from about 0.5 to 0.7.Type: ApplicationFiled: November 7, 2018Publication date: March 14, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ying Ting Hsia, Kun Yu Lin, Ying Ming Wang, Li-Te Hsu
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Patent number: 10141443Abstract: Semiconductor devices, FinFET devices with optimized strained-source-drain recess profiles and methods of forming the same are provided. One of the semiconductor devices includes a substrate, a gate stack over the substrate and a strained layer in a recess of the substrate and aside the gate stack. Besides, a ratio of a depth at the greatest width of the recess to a width of the gate stack ranges from about 0.5 to 0.7.Type: GrantFiled: March 24, 2016Date of Patent: November 27, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ying Ting Hsia, Kun Yu Lin, Ying Ming Wang, Li-Te Hsu
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Publication number: 20170278972Abstract: Semiconductor devices, FinFET devices with optimized strained-source-drain recess profiles and methods of forming the same are provided. One of the semiconductor devices includes a substrate, a gate stack over the substrate and a strained layer in a recess of the substrate and aside the gate stack. Besides, a ratio of a depth at the greatest width of the recess to a width of the gate stack ranges from about 0.5 to 0.7.Type: ApplicationFiled: March 24, 2016Publication date: September 28, 2017Inventors: Ying Ting Hsia, Kun Yu Lin, Ying Ming Wang, Li-Te Hsu
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Patent number: 7016410Abstract: A method for determining quantization numbers for each macro block in one video segment having a prescribed capacity is disclosed. The quantization numbers determine how much data will be preserved for that macro block. The method begins by determining a level of complexity for each macro block. Next, initial quantization numbers are chosen for the macro blocks by choosing the largest values possible without exceeding the prescribed capacity of the video segment. Final quantization numbers are selected based on respective ones of the initial quantization numbers proportioned according to the level of complexity for that macro block. The final quantization numbers may be increased or decreased so that the capacity of the video segment is maximized but not exceeded.Type: GrantFiled: August 23, 2002Date of Patent: March 21, 2006Assignee: ESS Technology, Inc.Inventors: Michael Chang, Ying-Ming Wang, Tai Jing
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Publication number: 20040037356Abstract: A method for determining quantization numbers for each macro block in one video segment having a prescribed capacity is disclosed. The quantization numbers determine how much data will be preserved for that macro block. The method begins by determining a level of complexity for each macro block. Next, initial quantization numbers are chosen for the macro blocks by choosing the largest values possible without exceeding the prescribed capacity of the video segment. Final quantization numbers are selected based on respective ones of the initial quantization numbers proportioned according to the level of complexity for that macro block. The final quantization numbers may be increased or decreased so that the capacity of the video segment is maximized but not exceeded.Type: ApplicationFiled: August 23, 2002Publication date: February 26, 2004Inventors: Michael Chang, Ying-Ming Wang, Tai Jing