Abstract: Disclosed are an array substrate, a display panel and a display apparatus. The array substrate includes: gate lines, data lines, and pixel units. The gate lines and the data lines are arranged between at least part of the adjacent pixel units. The array substrate further includes: common electrode lead wires and common electrode layers. The common electrode lead wires are arranged on a same layer as the data lines, extend in a same direction as the data lines, and are located between at least part of the adjacent pixel units. The common electrode layers are insulated from the common electrode lead wires through insulating layers and are connected with the common electrode lead wires through via holes in the insulating layers. The via holes are located in a region where the gate lines and the common electrode lead wires intersect.

Abstract: A light emitting diode and a driving method thereof, a light source apparatus, and an electronic device are disclosed, relating to the technical field of semiconductors. The light emitting diode includes: a substrate; a reflective light-emitting layer disposed on the substrate; a first electrode, a second electrode, and a first insulating layer which are discretely disposed on the reflective light-emitting layer; a saturable absorber layer disposed on the first insulating layer; and a third electrode, a fourth electrode, and a reflective composite layer which are disposed on the saturable absorber layer, respectively, the reflectivity of the reflective light-emitting layer is greater than the reflectivity of the reflective composite layer; wherein the orthographic projections of the saturable absorber layer, the third electrode, the fourth electrode, and the reflective composite layer on the reflective light-emitting layer, respectively, do not overlap with the first electrode and the second electrode.

Abstract: A color filter substrate, a manufacturing method thereof and a display device are disclosed. The color filter substrate includes a base substrate and a plurality of filter units located on the base substrate. Each filter unit includes a photonic crystal layer configured to transmit light of one color, and includes a first photonic crystal sub-layer and a second photonic crystal sub-layer that are stacked in a direction perpendicular to the base substrate.

Abstract: Disclosed are an array substrate, a display panel and a display apparatus. The array substrate includes: gate lines, data lines, and pixel units. The gate lines and the data lines are arranged between at least part of the adjacent pixel units. The array substrate further includes: common electrode lead wires and common electrode layers. The common electrode lead wires are arranged on a same layer as the data lines, extend in a same direction as the data lines, and are located between at least part of the adjacent pixel units. The common electrode layers are insulated from the common electrode lead wires through insulating layers and are connected with the common electrode lead wires through via holes in the insulating layers. The via holes are located in a region where the gate lines and the common electrode lead wires intersect.

Abstract: The present disclosure discloses a color filter substrate, a manufacture method thereof and a display device. The color filter substrate includes a substrate; and a light channel layer on a side of the substrate. The light channel layer includes a first photonic crystal layer and a second photonic crystal layer stacked with each other up and down. The light channel layer includes a plurality of light channel units formed by a periodic arrangement of three different primary-color light channel units. Each of the light channel units includes a photonic crystal block of the first photonic crystal layer and a photonic crystal block of the second photonic crystal layer with an orthographic projection of the photonic crystal block of the first photonic crystal layer on the substrate overlapping an orthographic projection of the photonic crystal block of the second photonic crystal layer on the substrate.

Abstract: Embodiments of the present disclosure provide a shift register unit and a driving method thereof, a gate driving circuit and a display device. The shift register unit comprises a shift register and a potential stabilizing circuit. The potential stabilizing circuit is configured to provide a signal from the reference signal terminal to the pulling-up node and the outputting signal terminal respectively, under a control of the potential stabilizing controlling terminal.

Abstract: A display substrate and a manufacturing method thereof and a display panel. The display substrate includes a display area and a reflective layer, and at least a portion of the reflective layer is in the display area. The reflective layer includes a metasurface facing a display side of the display substrate, and the metasurface includes a plurality of convex structures which have metamaterial properties and are scattered.

Abstract: A display substrate and a manufacturing method thereof and a display panel. The display substrate includes a display area and a reflective layer, and at least a portion of the reflective layer is in the display area. The reflective layer includes a metasurface facing a display side of the display substrate, and the metasurface includes a plurality of convex structures which have metamaterial properties and are scattered.

Abstract: Embodiments of the present disclosure provide a shift register unit and a driving method thereof, a gate driving circuit and a display device. The shift register unit comprises a shift register and a potential stabilizing circuit. The potential stabilizing circuit is configured to provide a signal from the reference signal terminal to the pulling-up node and the outputting signal terminal respectively, under a control of the potential stabilizing controlling terminal.

Abstract: There is provided in embodiments of the present disclosure a resource allocation method, apparatus, system, an electronic device and storage medium. The resource allocation method includes: receiving a resource allocation request of a first terminal and determining a type of the resource allocation request; feeding back an allocation result of an allocation of a first resource to the first terminal and a second terminal respectively, according to the type of the resource allocation request; acquiring feedback information about the allocation result from at least one of the first terminal and the second terminal; feeding back to the first terminal information about whether to modify the allocated first resource to a second resource, according to the feedback information.

Abstract: A color filter substrate, a manufacturing method thereof and a display device are disclosed. The color filter substrate includes a base substrate and a plurality of filter units located on the base substrate. Each filter unit includes a photonic crystal layer configured to transmit light of one color, and includes a first photonic crystal sub-layer and a second photonic crystal sub-layer that are stacked in a direction perpendicular to the base substrate.

Abstract: A shift register unit is disclosed which includes an input module, a reset module, a node control module, a first output module and a second output module. Each of the shift register units can output two scan signals that have a phase difference with respect to each other. Also disclosed are a gate driver circuit and a display device.

Abstract: The present application discloses a shift register unit circuit including an input port for receiving an input signal, an output port for outputting a gate driving signal, a first clock input port for receiving a first clock signal, a second clock input port for receiving a second clock signal, a pull-up node, a first pull-down node, a second pull-down node, a pull-up control sub-circuit connected to the input port and the pull-up node, a pull-up sub-circuit connected to the first clock input port and the pull-up node, a pull-down control sub-circuit connected to the first clock input port, a pull-down sub-circuit connected to the first pull-down node and the second pull-down node, a reset sub-circuit receiving a reset signal to control the potential level at the second pull-down node, and an initialization sub-circuit configured to receive an enabling signal for pulling-down the potential level at the second pull-down node.

Abstract: The present application discloses a gate driver on array (GOA) unit, including: a buffering module, a pull-up module, a pull-down module, a retaining module, a charging module, and a discharging module, a pull-up node being coupled to the buffering module, the discharging module, the pull-up module, and the charging module, and a pull-down node being coupled to the discharging module and the retaining module. The buffering module, being coupled to an input signal terminal and a pull-up node and controlled by a voltage of the input signal terminal, is configured to output the voltage of the input signal terminal into the pull-up node. The pull-up module, being coupled to a first clock signal terminal, the pull-up node, and an output signal terminal and controlled by a voltage of the pull-up node, is configured to output a voltage of the first clock signal terminal into the output signal terminal.

Abstract: A shift register and an operation method thereof. The shift register includes an input circuit, connected with an input terminal of the shift register and a pull-up node; a reset circuit, connected with a reset signal terminal, the pull-up node, a first power-supply voltage terminal, and an output terminal of the shift register; a pull-down control circuit, connected with a first clock signal terminal, the pull-up node, a pull-down node, and the first power-supply voltage terminal; a pull-down circuit, connected with the pull-down node, the output terminal of the shift register, the pull-up node, and the first power-supply voltage terminal; an output circuit, connected with the pull-up node, a second clock signal terminal, and the output terminal of the shift register; and a noise reduction circuit, connected with the pull-down node and configured for reducing noise at the output terminal.

Abstract: The present application discloses a shift register unit circuit including an input port for receiving an input signal, an output port for outputting a gate driving signal, a first clock input port for receiving a first clock signal, a second clock input port for receiving a second clock signal, a pull-up node, a first pull-down node, a second pull-down node, a pull-up control sub-circuit connected to the input port and the pull-up node, a pull-up sub-circuit connected to the first clock input port and the pull-up node, a pull-down control sub-circuit connected to the first clock input port, a pull-down sub-circuit connected to the first pull-down node and the second pull-down node, a reset sub-circuit receiving a reset signal to control the potential, level at the second pull-down node, and an initialization sub-circuit configured to receive an enabling signal for pulling-down the potential level at the second pull-down node.