Patents by Inventor Yingqiang YAN
Yingqiang YAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240136297Abstract: A multi-chip interconnection package structure with a heat dissipation plate and a preparation method thereof are provided. The multi-chip interconnection package structure with a heat dissipation plate includes a fine circuit layer, at least one die, a heat dissipation plate, a plastic package body, and a package circuit layer, the heat dissipation plate is provided on the fine circuit layer, and is mounted on a side of the die away from the fine circuit layer, the plastic package body wraps the die and the heat dissipation plate, and the package circuit layer is provided on the plastic package body.Type: ApplicationFiled: February 22, 2023Publication date: April 25, 2024Applicant: Institute of Semiconductors, Guangdong Academy of SciencesInventors: Yingqiang YAN, Chuan HU, Yao WANG, Wei ZHENG, Zhitao CHEN
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Publication number: 20240007072Abstract: A filter radio frequency module packaging structure and a method for manufacturing same is disclosed. A first filter chip of the filter radio frequency module packaging structure comprises a chip main body and a wall structure. The wall structure, the functional surface, and a substrate together define a closed cavity, or the wall structure and the functional surface together define a closed cavity. An encapsulation material wraps the first filter chip.Type: ApplicationFiled: July 27, 2021Publication date: January 4, 2024Applicant: INSTITUTE OF SEMICONDUCTORS, GUANGDONG ACADEMY OF SCIENCESInventors: Yingqiang YAN, Chuan HU, Xun XIANG, Wei ZHENG, Zhitao CHEN, Zhikuan CHEN
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Patent number: 11784625Abstract: A packaging method and package structure for a filter chip. The packaging method includes providing a circuit substrate, covering a first surface of the circuit substrate and/or filter chip with adhesive material and forming recessed cavities or closed cavities in the adhesive material. The method further includes adhering the filter chip to the first surface of circuit substrate via the adhesive material, such that surface acoustic wave transmitting regions of the filter chip correspond to the recessed cavities or closed cavities in the adhesive material to form a gap therebetween, and encapsulating the filter chip with encapsulating material. The method further includes forming interconnecting holes extending from a second surface of the circuit substrate to pins of the filter chip, filling the interconnecting holes with conductive material, so that the conductive material is in electrical contact with a chip pin bump or pad metal of the filter chip, and forming external pin pads on the second surface.Type: GrantFiled: December 11, 2019Date of Patent: October 10, 2023Assignee: GUANGDONG INSTITUTE OF SEMICONDUCTOR INDUSTRIAL TECHNOLOGYInventors: Yingqiang Yan, Chuan Hu, Zhitao Chen
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Publication number: 20230253333Abstract: Provided are a chip fine line fan-out package structure and a manufacturing method therefor. The chip fine line fan-out package structure provided and the chip fine line fan-out package structure manufactured using the manufacturing method each include an inter-chip fine winding layer and a package winding layer. The line width and line spacing of the inter-chip fine winding layer are less than the line width and line spacing of the package winding layer, and therefore, a user can choose to use different package winding layers according to actual needs. Therefore, the chip fine line fan-out package structure and the package structure manufactured using the manufacturing method can meet the use demands of users in more scenarios.Type: ApplicationFiled: July 27, 2020Publication date: August 10, 2023Applicant: GUANGDONG INSTITUTE OF SEMICONDUCTOR INDUSTRIAL TECHNOLOGYInventors: Yingqiang YAN, Yao WANG, Chuan HU, Xun XIANG, Zhitao CHEN
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Publication number: 20230245944Abstract: A fan-out type package and a preparation method of the fan-out type package are provided. The fan-out type package has one or more chips having same or different functions and each having a back surface mounted in a chip mounting region of the heat dissipation sheet via the adhesive material layer, and a front surface covered by a temporary protection material; an adhesive material layer; a heat dissipation sheet; an encapsulation material layer formed by making an encapsulation material flow into and fill a gap between the temporary protection material and the heat dissipation sheet and/or cover a side of the heat dissipation sheet opposite to a side thereof mounted with the chip, and then removing the temporary protection material; a packaging circuit grown on the front surface of the chip, the encapsulation material, and the heat dissipation sheet; and a packaging circuit protection layer protecting the packaging circuit.Type: ApplicationFiled: July 28, 2021Publication date: August 3, 2023Inventors: Yingqiang Yan, Chuan Hu, Zhikuan Chen, Zhitao Chen
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Patent number: 11710646Abstract: A fan-out packaging method includes: prepare circuit patterns on one side or both sides of a substrate; install electronic parts on one side or both sides of the substrate; prepare packaging layers on both sides of the substrate; the packaging layers on both sides of the substrate package the substrate, the circuit patterns, and the electronic parts, the packaging layers being made of a thermal-plastic material; wherein the substrate is provided with a via hole; both sides of the substrate are communicated by means of the via hole; a part of the packaging layers penetrate through the via hole when the packaging layers are prepared on both sides of the substrate; and the packaging layers on both sides of the substrate are connected by means of the via hole.Type: GrantFiled: October 11, 2018Date of Patent: July 25, 2023Assignee: SHENZHEN XIUYI INVESTMENT DEVELOPMENT PARTNERSHIP (LIMITED PARTNERSHIP)Inventors: Chuan Hu, Yingqiang Yan, Yuejin Guo, Yingjun Pi, Junjun Liu, Edward Prack
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Publication number: 20220149007Abstract: The present disclosure provides a chip packaging structure and method, using a back-to-back packaging structure, and realizing electrical connection between chips through TSV holes or cooperation between TSV and TMV holes, completely penetrating two chips. Thus, the TSV hole passing through a silicon material may not need to be formed in advance on the chips before bonding the chips, thereby the requirement of alignment accuracy of the chips can be reduced, and the process difficulty can be reduced. In addition, as the back-to-back packaging process is adopted, the heat dissipation efficiency of the chips can be improved, and the problem of circuit breakage due to materials with different expansion coefficients present between the chips can be avoided.Type: ApplicationFiled: June 16, 2020Publication date: May 12, 2022Inventors: Yuan BAO, Xun XIANG, Yao WANG, Yingqiang YAN, Chuan HU, Zhitao CHEN
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Publication number: 20220051908Abstract: A fan-out packaging method includes: prepare circuit patterns on one side or both sides of a substrate; install electronic parts on one side or both sides of the substrate; prepare packaging layers on both sides of the substrate; the packaging layers on both sides of the substrate package the substrate, the circuit patterns, and the electronic parts, the packaging layers being made of a thermal-plastic material; wherein the substrate is provided with a via hole; both sides of the substrate are communicated by means of the via hole; a part of the packaging layers penetrate through the via hole when the packaging layers are prepared on both sides of the substrate; and the packaging layers on both sides of the substrate are connected by means of the via hole.Type: ApplicationFiled: October 11, 2018Publication date: February 17, 2022Inventors: Chuan HU, Yingqiang YAN, Yuejin GUO, Yingjun PI, Junjun LIU, Edward PRACK
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Publication number: 20210358883Abstract: A fan-out packaging method employing a combined process includes: manufacturing at least two layers of basic circuit patterns on a substrate; manufacturing a galvanic isolation layer on one of the two layers of basic circuit patterns; manufacturing a fine circuit pattern on the galvanic isolation layer; using a bonding layer to bond an electronic component to the galvanic isolation layer, and using a patch material to establish an electrical connection between the electronic component and the fine circuit pattern; and using a packaging layer to package the electronic component, wherein the fine circuit pattern has a width less than widths of the basic circuit patterns. In the present disclosure, multiple layers of circuits are manufactured before installation and packaging of electronic components, thereby reducing the number of times an insulation material is to be heated, and broadening the range of available types of insulation materials.Type: ApplicationFiled: October 11, 2018Publication date: November 18, 2021Inventors: Chuan HU, Yingqiang YAN, Yuejin GUO, Yingjun PI, Junjun LIU
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Publication number: 20210184649Abstract: A packaging method and package structure for a filter chip. The packaging method includes providing a circuit substrate, covering a first surface of the circuit substrate and/or filter chip with adhesive material and forming recessed cavities or closed cavities in the adhesive material. The method further includes adhering the filter chip to the first surface of circuit substrate via the adhesive material, such that surface acoustic wave transmitting regions of the filter chip correspond to the recessed cavities or closed cavities in the adhesive material to form a gap therebetween, and encapsulating the filter chip with encapsulating material. The method further includes forming interconnecting holes extending from a second surface of the circuit substrate to pins of the filter chip, filling the interconnecting holes with conductive material, so that the conductive material is in electrical contact with a chip pin bump or pad metal of the filter chip, and forming external pin pads on the second surface.Type: ApplicationFiled: December 11, 2019Publication date: June 17, 2021Inventors: Yingqiang YAN, Chuan HU, Zhitao CHEN