Patents by Inventor Yingwu ZHANG

Yingwu ZHANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240093443
    Abstract: Disclosed in the present disclosure is a double-deck multi-span bridge construction method. According to the double-deck bridge construction method of the present disclosure, construction is carried out by using a method of disassembling a support jig frame in a graded and span-separated mode, an upper chord jig frame and a lower chord jig frame can be used in a recycle manner, and construction costs are reduced. In addition, a construction period of building the support jig frame is shortened, and other construction operations can be synchronously carried out on a span in which the jig frame is disassembled, for example, fire retardant coating construction can be carried out on a mounted bridge deck after the jig frame is disassembled, and the construction period of a double-deck multi-span bridge is effectively shortened.
    Type: Application
    Filed: September 23, 2021
    Publication date: March 21, 2024
    Applicant: CHINA CONSTRUCTION SCIENCE AND INDUSTRY CORPORATION LTD.
    Inventors: Jinglei REN, Bing SUN, Yonggang GAO, Hongyu SHEN, Shaohui ZHU, Jianguo QI, Cui LIU, Ruihua YAN, Zhiqiang HE, Longfei LI, Sijie YANG, Huaidong ZHANG, Xu CHEN, Wei JIANG, Wenbo LI, Yingwu SUN, Yuhang ZHANG
  • Publication number: 20240078200
    Abstract: Disclosed are a memory operating method, memory and electronic device. The memory complies with a read-write parallel protocol and includes a plurality of memory banks, and the method includes: sequentially mapping read and write transactions for consecutive logical addresses to different banks according to a predetermined transmission bit width by an address decoder, and arbitrating the read transaction and write transaction mapped to the same bank in a current clock cycle by an arbitration circuit, wherein in case that a specific low address bits of the logical address are the same, the read and/or the write transaction are mapped to the same bank. The disclosure avoids long-term occupation of a certain physical bank with specific low address decoding solution, thereby improving the execution efficiency of the read-write parallel protocol. Furthermore, an arbitration mechanism is introduced to arbitrate read and write conflicts for the same memory bank in each clock cycle.
    Type: Application
    Filed: April 27, 2023
    Publication date: March 7, 2024
    Inventors: Ze HE, Nanfei WANG, Yingwu ZHANG