Abstract: A data processing host includes a program running environment and a first isolation environment. The first isolation environment is isolated from the program running environment. The host operates in a non-secure mode in the program running environment, and operates in a secure mode in the first isolation environment. The program running environment includes a virtual instance operating in the non-secure mode, and the first isolation environment corresponds to the virtual instance in the program running environment. The first isolation environment includes an operating system in the secure mode and a resource allocated to the first isolation environment and comprising a first isolation space for running the operation system and a secure processing program, which corresponds to a program in the virtual instance and is for processing to-be-processed data.

Abstract: Butyl rubber, a preparation method therefor, and an application thereof, and a composition and rubber product containing the butyl rubber. The butyl rubber comprises a structural unit derived from isobutylene, a structural unit derived from conjugated diene, and a structural unit selectively derived from aryl olefin represented by formula I, at least a part of the conjugated diene being isoprene. Also provided are an automobile tire inner liner, tube and curing bladder made of the butyl rubber. The butyl rubber has good processability and compounding properties, die swell ratio and integrated mechanical properties, and particularly high tear strength. The butyl rubber can effectively reduce power consumption in the processing and compounding process, and the prepared product has good dimensional stability and application performance.

Abstract: Butyl rubber, a preparation method therefor, and an application thereof, and a composition and rubber product containing the butyl rubber. The butyl rubber comprises a structural unit derived from isobutylene, a structural unit derived from conjugated diene, and a structural unit selectively derived from aryl olefin represented by formula I, at least a part of the conjugated diene being isoprene. Also provided are an automobile tire inner liner, tube and curing bladder made of the butyl rubber. The butyl rubber has good processability and compounding properties, die swell ratio and integrated mechanical properties, and particularly high tear strength. The butyl rubber can effectively reduce power consumption in the processing and compounding process, and the prepared product has good dimensional stability and application performance.

Abstract: The present invention provides a tunneling field effect transistor and a method for fabricating the same which refer to a field effect transistor logic device and circuit in a CMOS ultra-large integrated circuit (ULSI). The inventive concept of the invention lies in that, in a case of an N-type transistor, a side portion of a doped source region adjacent to an edge of the control gate is further implanted with P+ impurities on a basis of the doped source region being initially doped N? impurities, so that the initial N? impurities in the implanted portion are completely compensated by the P+ impurities, and in a case of a P-type transistor, a side portion of the doped source region adjacent to an edge of the control gate is implanted with N+ impurities on a basis of the doped source region being initially doped P? impurities, so that the initial P? impurities in the implanted portion are completely compensated by the N+ impurities.

Abstract: The present invention provides a tunneling field effect transistor and a method for fabricating the same which refer to a field effect transistor logic device and circuit in a CMOS ultra-large integrated circuit (ULSI). The inventive concept of the invention lies in that, in a case of an N-type transistor, a side portion of a doped source region adjacent to an edge of the control gate is further implanted with P+ impurities on a basis of the doped source region being initially doped N? impurities, so that the initial N? impurities in the implanted portion are completely compensated by the P+ impurities, and in a case of a P-type transistor, a side portion of the doped source region adjacent to an edge of the control gate is implanted with N+ impurities on a basis of the doped source region being initially doped P? impurities, so that the initial P? impurities in the implanted portion are completely compensated by the N+ impurities.

Abstract: The present invention discloses a strip-shaped gate-modulated tunneling field effect transistor with double-diffusion and a preparation method thereof, belonging to a field of CMOS field effect transistor logic device and the circuit.

Abstract: The present invention discloses a strip-shaped gate-modulated tunneling field effect transistor and a preparation method thereof, belonging to a field of field effect transistor logic device and the circuit in CMOS ultra large scale integrated circuit (ULSI). The tunneling field effect transistor includes a control gate, a gate dielectric layer, a semiconductor substrate, a highly-doped source region and a highly-doped drain region, where the highly-doped source region and the highly-doped drain region lie on both sides of the control gate, respectively, the control gate has a strip-shaped structure with a gate length greater than a gate width, and at one side thereof is connected to the highly-doped drain region and at the other side thereof extends laterally into the highly-doped source region; a region located below the control gate is a channel region; and the gate width of the control gate is less than twice width of a source depletion layer.

Abstract: The present invention discloses a strip-shaped gate-modulated tunneling field effect transistor with double-diffusion and a preparation method thereof, belonging to a field of CMOS field effect transistor logic device and the circuit.

Abstract: Disclosed herein is a method for fabricating a complementary tunneling field effect transistor based on a standard CMOS IC process, which belongs to the field of logic devices and circuits of field effect transistors in ultra large scaled integrated (ULSI) circuits. In the method, an intrinsic channel and body region of a TFET are formed by means of complementary P-well and N-well masks in the standard CMOS IC process to form a well doping, a channel doping and a threshold adjustment by implantation. Further, a bipolar effect in the TFET can be inhibited via a distance between a gate and a drain on a layout so that a complementary TFET is formed. In the method according to the invention, the complementary tunneling field effect transistor (TFET) can be fabricated by virtue of existing processes in the standard CMOS IC process without any additional masks and process steps.

Abstract: Disclosed herein is a method for fabricating a complementary tunneling field effect transistor based on a standard CMOS IC process, which belongs to the field of logic devices and circuits of field effect transistors in ultra large scaled integrated (ULSI) circuits. In the method, an intrinsic channel and body region of a TFET are formed by means of complementary P-well and N-well masks in the standard CMOS IC process to form a well doping, a channel doping and a threshold adjustment by implantation. Further, a bipolar effect in the TFET can be inhibited via a distance between a gate and a drain on a layout so that a complementary TFET is formed. In the method according to the invention, the complementary tunneling field effect transistor (TFET) can be fabricated by virtue of existing processes in the standard CMOS IC process without any additional masks and process steps.

Abstract: The present invention discloses a strip-shaped gate-modulated tunneling field effect transistor and a preparation method thereof, belonging to a field of field effect transistor logic device and the circuit in CMOS ultra large scale integrated circuit (ULSI). The tunneling field effect transistor includes a control gate, a gate dielectric layer, a semiconductor substrate, a highly-doped source region and a highly-doped drain region, where the highly-doped source region and the highly-doped drain region lie on both sides of the control gate, respectively, the control gate has a strip-shaped structure with a gate length greater than a gate width, and at one side thereof is connected to the highly-doped drain region and at the other side thereof extends laterally into the highly-doped source region; a region located below the control gate is a channel region; and the gate width of the control gate is less than twice width of a source depletion layer.