Patents by Inventor Yingyi Ju

Yingyi Ju has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • METHOD AND STORAGE DEVICE FOR PARALLELLY PROCESSING THE DEALLOCATION COMMAND
    Publication number: 20220327049
    Abstract: The present application discloses a method for processing a deallocation command and a storage device thereof. The disclosed method includes the following steps: in response to receiving the deallocation command, obtaining an address range indicated by the deallocation command; and updating the table items of the deallocation table according to the address range indicated by the deallocation command. Embodiments of the present application can reduce the delay in processing the deallocation command and reduce the impact of processing the deallocation command on the processing bandwidth of the IO command.
    Type: Application
    Filed: June 22, 2022
    Publication date: October 13, 2022
    Inventors: Yingyi JU, Rong YUAN, Baoyong SUN, Zhihong GUO, Huijuan GAO, Shunan CAI
  • Deallocating command processing method and storage device having multiple CPUs thereof
    Patent number: 11397672
    Abstract: The present application discloses a method for processing a deallocation command and a storage device thereof. The disclosed method includes the following steps: in response to receiving the deallocation command, obtaining an address range indicated by the deallocation command; and updating the table items of the deallocation table according to the address range indicated by the deallocation command. Embodiments of the present application can reduce the delay in processing the deallocation command and reduce the impact of processing the deallocation command on the processing bandwidth of the IO command.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: July 26, 2022
    Assignee: BEIJING MEMBLAZE TECHNOLOGY CO., LTD
    Inventors: Yingyi Ju, Rong Yuan, Baoyong Sun, Zhihong Guo, Huijuan Gao, Shunan Cai
  • DEALLOCATING COMMAND PROCESSING METHOD AND STORAGE DEVICE THEREOF
    Publication number: 20210103518
    Abstract: The present application discloses a method for processing a deallocation command and a storage device thereof. The disclosed method includes the following steps: in response to receiving the deallocation command, obtaining an address range indicated by the deallocation command; and updating the table items of the deallocation table according to the address range indicated by the deallocation command. Embodiments of the present application can reduce the delay in processing the deallocation command and reduce the impact of processing the deallocation command on the processing bandwidth of the IO command.
    Type: Application
    Filed: June 28, 2018
    Publication date: April 8, 2021
    Inventors: Yingyi JU, Rong YUAN, Baoyong SUN, Zhihong GUO, Huijuan GAO, Shunan CAI
  • Read disturb handling in NAND flash
    Patent number: 9229642
    Abstract: An apparatus having a processor and an interface to a nonvolatile memory having a plurality of blocks is disclosed. The processor is configured to (i) monitor a number of reads since a respective erase in at least one of the blocks in the nonvolatile memory, (ii) move a page from a first block to a second block in response to the number of reads exceeding a first threshold where the first block is partially programmed and (iii) move the page from the first block to the second block in response to the number of reads exceeding a second threshold where the first block is fully programmed. The first threshold is less than the second threshold.
    Type: Grant
    Filed: April 2, 2014
    Date of Patent: January 5, 2016
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Nanshan Shu, Peng Xu, Zhimin Dong, Yingyi Ju, Jiangang Wu
  • READ DISTURB HANDLING IN NAND FLASH
    Publication number: 20150268871
    Abstract: An apparatus having a processor and an interface to a nonvolatile memory having a plurality of blocks is disclosed. The processor is configured to (i) monitor a number of reads since a respective erase in at least one of the blocks in the nonvolatile memory, (ii) move a page from a first block to a second block in response to the number of reads exceeding a first threshold where the first block is partially programmed and (iii) move the page from the first block to the second block in response to the number of reads exceeding a second threshold where the first block is fully programmed. The first threshold is less than the second threshold.
    Type: Application
    Filed: April 2, 2014
    Publication date: September 24, 2015
    Applicant: LSI Corporation
    Inventors: Nanshan Shu, Peng Xu, Zhimin Dong, Yingyi Ju, Jiangang Wu