Abstract: An apparatus to facilitate deep learning numeric data and sparse matrix compression is disclosed. The apparatus includes a processor comprising a compression engine to: receive a data packet comprising a plurality of cycles of data samples, and for each cycle of the data samples: pass the data samples of the cycle to a compressor dictionary; identify, from the compressor dictionary, tags for each of the data samples, wherein the compressor dictionary comprises at least a first tag for data having a value of zero and a second tag for data having a value of one; and compress the data samples into compressed cycle data by storing the tags as compressed data, wherein the data samples identified with the first tag are compressed using the first tag and the data samples identified with the second tag are compressed using the second tag at the same time as values of the data samples identified with the first tag or the second tag are excluded from the compressed cycle data.

Abstract: An apparatus and method is provided that compensates for the supply droops to minimize strobe shifts and to regain eye margin. The apparatus includes a droop detector to detect voltage droops at one or more trip (or threshold) levels and these detected voltage droops are translated to a shift in clock phase setting. For example, propagation delay of a delay locked loop (DLL) and/or clock edge selection from a phase interpolator (PI) is adjusted according to the detected voltage droop levels to maintain a trained relationship between the sampling clock strobe and data eye. A lookup table is used to determine a PI code or a DLL propagation delay code corresponding to a voltage droop level.

Abstract: A processing device includes a package, a plurality of dies disposed on the package, where each die comprises a clock receiver, and a single common clock source to generate a common clock signal. The processing device also includes a clock distribution circuitry coupled to the single common clock source. The clock distribution circuitry distributes the common clock signal from the single common clock source to each of the plurality of dies individually. The clock distribution circuitry includes a first group of terminated transmission lines. The first group of terminated transmission lines includes a first terminated transmission line, a second terminated transmission line, and a first termination resistor coupled between the first terminated transmission line and the second terminated transmission line. The first terminated transmission line and the second terminated transmission line receive the common clock signal from the single common clock source.