Patents by Inventor Yinjie Ding

Yinjie Ding has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10797223
    Abstract: Integrated circuits with magnetic random access memory (MRAM) devices and methods for fabricating such devices are provided. In an exemplary embodiment, a method for fabricating MRAM bitcells includes determining a desired inter-cell spacing between a first bitcell and a second bitcell and double patterning a semiconductor substrate to form semiconductor fin structures, wherein the semiconductor fin structures are formed in groups with an intra-group pitch between grouped semiconductor fin structures and with the inter-cell spacing between adjacent groups of semiconductor fin structures different from the intra-group pitch. The method further includes forming a first MRAM memory structure over the semiconductor fin structures in the first bitcell and forming a second MRAM memory structure over the semiconductor fin structures in the second bitcell. Also, the method includes forming a first source line for the first bitcell between the first MRAM memory structure and the second MRAM memory structure.
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: October 6, 2020
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Bin Liu, Eng Huat Toh, Yinjie Ding, Kangho Lee, Elgin Kiok Boone Quek
  • Publication number: 20190237658
    Abstract: Integrated circuits with magnetic random access memory (MRAM) devices and methods for fabricating such devices are provided. In an exemplary embodiment, a method for fabricating MRAM bitcells includes determining a desired inter-cell spacing between a first bitcell and a second bitcell and double patterning a semiconductor substrate to form semiconductor fin structures, wherein the semiconductor fin structures are formed in groups with an intra-group pitch between grouped semiconductor fin structures and with the inter-cell spacing between adjacent groups of semiconductor fin structures different from the intra-group pitch. The method further includes forming a first MRAM memory structure over the semiconductor fin structures in the first bitcell and forming a second MRAM memory structure over the semiconductor fin structures in the second bitcell. Also, the method includes forming a first source line for the first bitcell between the first MRAM memory structure and the second MRAM memory structure.
    Type: Application
    Filed: January 29, 2018
    Publication date: August 1, 2019
    Inventors: Bin Liu, Eng Huat Toh, Yinjie Ding, Kangho Lee, Elgin Kiok Boone Quek
  • Patent number: 10217828
    Abstract: A method of forming a bulk transistor integrated with silicon-on-insulator (SOI) field plates, and related device, are provided. Embodiments include forming a silicon-on-insulator (SOI) substrate as a field plate on a field plate oxide; forming a high-voltage p-type well in a p-type substrate of a bulk transistor on which the SOI substrate is formed, the high-voltage p-type formed between shallow trench isolation (STI) region of the p-type substrate; forming an n-drift region in the high-voltage p-type well; forming a first gate on the high-voltage p-type well; and implanting a first n-type region adjacent to the gate as a source region and a second n-type region adjacent to the SOI substrate as a drain region.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: February 26, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Yinjie Ding, Eng Huat Toh, Shyue Seng Tan
  • Publication number: 20180374893
    Abstract: A method of forming a differential sensing STT MRAM design and the resulting device are provided. Embodiments include rows of programmable cells formed in a magnetoresistive random-access memory (MRAM) device, each row having a source line (SL); and rows of complimentary cells formed in the MRAM device, each row having a SL, wherein a SL of a row of programmable cells and a SL of a row of complimentary cells of a pair of rows form a merged SL.
    Type: Application
    Filed: June 22, 2017
    Publication date: December 27, 2018
    Inventors: Eng Huat TOH, Yinjie DING, Kangho LEE
  • Patent number: 10121959
    Abstract: A method of forming a segmented FDSOI STT-MRAM using dummy WL blocks and the resulting device are provided. Embodiments include forming a plurality of FDSOI STT-MRAM active WL blocks laterally separated across a memory array; forming a FDSOI STT-MRAM dummy WL block parallel to and on opposite sides of each active WL block; forming a plurality of SL structures laterally separated across the memory array; forming a plurality of BL structures laterally separated across the memory array; and connecting the plurality of SL and BL structures to the plurality of active WL blocks.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: November 6, 2018
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Yinjie Ding, Eng Huat Toh, Kangho Lee, Elgin Kiok Boone Quek