Patents by Inventor Yip Seng Low
Yip Seng Low has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11335659Abstract: Various semiconductor chip solder bump and underbump metallization (UBM) structures and methods of making the same are disclosed. In one aspect, a method is provided that includes forming a first underbump metallization layer on a semiconductor chip is provided. The first underbump metallization layer has a hub, a first portion extending laterally from the hub, and a spoke connecting the hub to the first portion. A polymer layer is applied to the first underbump metallization layer. The polymer layer includes a first opening in alignment with the hub and a second opening in alignment with the spoke. A portion of the spoke is removed via the second opening to sever the connection between the hub and the first portion.Type: GrantFiled: December 30, 2016Date of Patent: May 17, 2022Assignee: ATI TECHNOLOGIES ULCInventors: Roden R. Topacio, Suming Hu, Yip Seng Low
-
Patent number: 9793199Abstract: Various circuit boards and methods of manufacturing the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first interconnect layer of a circuit board. The first interconnect layer includes a first conductor trace with a first segment that does not include a via land. A first via is formed on the first segment.Type: GrantFiled: December 18, 2009Date of Patent: October 17, 2017Assignee: ATI Technologies ULCInventors: Andrew K W Leung, Neil McLellan, Yip Seng Low
-
Publication number: 20170110428Abstract: Various semiconductor chip solder bump and underbump metallization (UBM) structures and methods of making the same are disclosed. In one aspect, a method is provided that includes forming a first underbump metallization layer on a semiconductor chip is provided. The first underbump metallization layer has a hub, a first portion extending laterally from the hub, and a spoke connecting the hub to the first portion. A polymer layer is applied to the first underbump metallization layer. The polymer layer includes a first opening in alignment with the hub and a second opening in alignment with the spoke. A portion of the spoke is removed via the second opening to sever the connection between the hub and the first portion.Type: ApplicationFiled: December 30, 2016Publication date: April 20, 2017Inventors: Roden R. Topacio, Suming Hu, Yip Seng Low
-
Patent number: 9576923Abstract: Various semiconductor chip solder bump and underbump metallization (UBM) structures and methods of making the same are disclosed. In one aspect, a method is provided that includes forming a first underbump metallization layer on a semiconductor chip is provided. The first underbump metallization layer has a hub, a first portion extending laterally from the hub, and a spoke connecting the hub to the first portion. A polymer layer is applied to the first underbump metallization layer. The polymer layer includes a first opening in alignment with the hub and a second opening in alignment with the spoke. A portion of the spoke is removed via the second opening to sever the connection between the hub and the first portion.Type: GrantFiled: April 1, 2014Date of Patent: February 21, 2017Assignee: ATI Technologies ULCInventors: Roden R. Topacio, Suming Hu, Yip Seng Low
-
Publication number: 20150279794Abstract: Various semiconductor chip solder bump and underbump metallization (UBM) structures and methods of making the same are disclosed. In one aspect, a method is provided that includes forming a first underbump metallization layer on a semiconductor chip is provided. The first underbump metallization layer has a hub, a first portion extending laterally from the hub, and a spoke connecting the hub to the first portion. A polymer layer is applied to the first underbump metallization layer. The polymer layer includes a first opening in alignment with the hub and a second opening in alignment with the spoke. A portion of the spoke is removed via the second opening to sever the connection between the hub and the first portion.Type: ApplicationFiled: April 1, 2014Publication date: October 1, 2015Inventors: Roden R. Topacio, Suming Hu, Yip Seng Low
-
Patent number: 8772083Abstract: Various substrates or circuit boards for receiving a semiconductor chip and methods of processing the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first opening in a solder mask positioned on a side of a substrate. The first opening does not extend to the side. A second opening is formed in the solder mask that extends to the side. The first opening may serve as an underfill anchor site.Type: GrantFiled: September 10, 2011Date of Patent: July 8, 2014Assignees: ATI Technologies ULC, Advanced Micro Devices, Inc.Inventors: Andrew K W Leung, Roden R. Topacio, Yu-Ling Hsieh, Yip Seng Low
-
Patent number: 8637983Abstract: An integrated circuit (IC) product includes a redistribution layer (RDL) having at least one conductive layer configured to distribute electrical information from one location to another location in the IC. The RDL also includes a plurality of wire bond pads and a plurality of solder pads. The plurality of solder pads each includes a solder wettable material that is in direct electrical communication with the RDL.Type: GrantFiled: December 19, 2008Date of Patent: January 28, 2014Assignee: ATI Technologies ULCInventors: Liane Martinez, Roden R. Topacio, Yip Seng Low
-
Patent number: 8564122Abstract: Various circuit boards and methods of fabricating the same are disclosed. In one aspect, a method of manufacturing is provided that includes coupling an electrically non-functional component to a surface of a first circuit board. The electrically non-functional component has a first elevation. The surface of the circuit board is adapted to have a semiconductor chip mounted thereon. An electrically functional component is mounted to the surface inward from the electrically non-functional component. The electrically functional component has a second elevation less than the first elevation.Type: GrantFiled: December 9, 2011Date of Patent: October 22, 2013Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Neil R. McLellan, Liane Martinez, Yip Seng Low, Suming Hu
-
Publication number: 20130258610Abstract: Various circuit board lids and methods and using the same are disclosed. In one aspect, an apparatus is provided that includes a lid adapted to cover a semiconductor chip mounted on a circuit board. The lid has a top plate, a first support leg and a second support leg opposite the first support leg adapted to support the lid. The first and second support legs and the top plate define a recess to accommodate the semiconductor chip. The recess has a first opening and a second opening. At least one of the first and second openings extends from the first support leg to the second support leg.Type: ApplicationFiled: March 29, 2012Publication date: October 3, 2013Inventors: Jianguo Li, Neil McLellan, Yip Seng Low
-
Publication number: 20130147012Abstract: Various circuit boards and methods of fabricating the same are disclosed. In one aspect, a method of manufacturing is provided that includes coupling an electrically non-functional component to a surface of a first circuit board. The electrically non-functional component has a first elevation. The surface of the circuit board is adapted to have a semiconductor chip mounted thereon. An electrically functional component is mounted to the surface inward from the electrically non-functional component. The electrically functional component has a second elevation less than the first elevation.Type: ApplicationFiled: December 9, 2011Publication date: June 13, 2013Inventors: Neil R. McLellan, Liane Martinez, Yip Seng Low, Suming Hu
-
Publication number: 20130147026Abstract: According an embodiment, a package-on-package heatsink interposer for use between a top package and a bottom package of a package-on-package device, may include a top heatsink below the top package; an interposer substrate below the top heatsink; a bottom heatsink below the interposer substrate; a first interposer substrate metal layer between the interposer substrate and the top heatsink; a second interposer substrate metal layer between the interposer substrate and the bottom heatsink; and interposer solder balls between the second interposer substrate metal layer and the bottom package.Type: ApplicationFiled: December 12, 2011Publication date: June 13, 2013Applicant: ATI Technologies ULCInventors: Roden R. TOPACIO, Liane Martinez, Yip Seng Low
-
Publication number: 20130113084Abstract: Various semiconductor substrates and methods of processing the same are disclosed. In one aspect, a method of manufacturing is provided that includes mounting a first semiconductor chip on a side of a first substrate. The first substrate has at least one thru-silicon-via. An insulating layer is molded on the side of the first substrate. The insulating layer provides a support structure to enable handling of the first substrate.Type: ApplicationFiled: November 4, 2011Publication date: May 9, 2013Inventors: Roden R. Topacio, Neil McLellan, Yip Seng Low, Jianguo Li
-
Publication number: 20130062786Abstract: Various substrates or circuit boards for receiving a semiconductor chip and methods of processing the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first opening in a solder mask positioned on a side of a substrate. The first opening does not extend to the side. A second opening is formed in the solder mask that extends to the side. The first opening may serve as an underfill anchor site.Type: ApplicationFiled: September 10, 2011Publication date: March 14, 2013Inventors: Andrew KW Leung, Roden R. Topacio, Yu-Ling Hsieh, Yip Seng Low
-
Patent number: 8298945Abstract: A method of manufacturing a substrate for use in electronic packaging having a core, m buildup layers on a first surface of the core and n buildup layers on a second surface of the core, where m?n is disclosed. The method includes forming (m?n) of the m buildup layers on the first surface, and then forming n pairs of buildup layers, with each one of the pairs including one of the n buildup layers formed on the second surface and one of the remaining n of the m buildup layers formed on the first surface. Each buildup layer includes a dielectric layer and a conductive layer formed thereon. The disclosed method protects the dielectric layer in each of buildup layers from becoming overdesmeared during substrate manufacturing by avoiding repeated desmearing of dielectric materials.Type: GrantFiled: June 3, 2011Date of Patent: October 30, 2012Assignee: ATI Technologies ULCInventors: Andrew Leung, Roden R. Topacio, Liane Martinez, Yip Seng Low
-
Patent number: 8294266Abstract: Various semiconductor die conductor structures and methods of fabricating the same are provided. In one aspect, a method of manufacturing is provided that includes forming a conductor structure on a conductor pad of a semiconductor die. The conductor layer has a surface. A polymeric layer is formed on the surface of the conductor layer while a portion of the surface is left exposed. A solder structure is formed on the exposed portion of the surface and a portion of the polymeric layer.Type: GrantFiled: February 14, 2011Date of Patent: October 23, 2012Assignee: Advanced Micro Devices, Inc.Inventors: Roden R. Topacio, Neil McLellan, Yip Seng Low, Andrew K W Leung
-
Publication number: 20120120615Abstract: Various circuit boards and methods of manufacturing the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first interconnect layer of a circuit board. The first interconnect layer includes a first conductor trace with a first segment that does not include a via land. A first via is formed on the first segment.Type: ApplicationFiled: January 23, 2012Publication date: May 17, 2012Inventors: Andrew KW Leung, Neil McLellan, Yip Seng Low
-
Publication number: 20110225813Abstract: A method of manufacturing a substrate for use in electronic packaging having a core, m buildup layers on a first surface of the core and n buildup layers on a second surface of the core, where m?n is disclosed. The method includes forming (m?n) of the m buildup layers on the first surface, and then forming n pairs of buildup layers, with each one of the pairs including one of the n buildup layers formed on the second surface and one of the remaining n of the m buildup layers formed on the first surface. Each buildup layer includes a dielectric layer and a conductive layer formed thereon. The disclosed method protects the dielectric layer in each of buildup layers from becoming overdesmeared during substrate manufacturing by avoiding repeated desmearing of dielectric materials.Type: ApplicationFiled: June 3, 2011Publication date: September 22, 2011Applicant: ATI TECHNOLOGIES ULCInventors: Andrew Leung, Roden Topacio, Liane Martinez, Yip Seng Low
-
Publication number: 20110147061Abstract: Various circuit boards and methods of manufacturing the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first interconnect layer of a circuit board. The first interconnect layer includes a first conductor trace with a first segment that does not include a via land. A first via is formed on the first segment.Type: ApplicationFiled: December 18, 2009Publication date: June 23, 2011Inventors: Andrew K.W. Leung, Neil McLellan, Yip Seng Low
-
Publication number: 20110133338Abstract: Various semiconductor die conductor structures and methods of fabricating the same are provided. In one aspect, a method of manufacturing is provided that includes forming a conductor structure on a conductor pad of a semiconductor die. The conductor layer has a surface. A polymeric layer is formed on the surface of the conductor layer while a portion of the surface is left exposed. A solder structure is formed on the exposed portion of the surface and a portion of the polymeric layer.Type: ApplicationFiled: February 14, 2011Publication date: June 9, 2011Inventors: Roden R. Topacio, Neil McLellan, Yip Seng Low, Andrew KW Leung
-
Patent number: 7906424Abstract: Various semiconductor die conductor structures and methods of fabricating the same are provided. In one aspect, a method of manufacturing is provided that includes forming a conductor structure on a conductor pad of a semiconductor die. The conductor layer has a surface. A polymeric layer is formed on the surface of the conductor layer while a portion of the surface is left exposed. A solder structure is formed on the exposed portion of the surface and a portion of the polymeric layer.Type: GrantFiled: August 1, 2007Date of Patent: March 15, 2011Assignee: Advanced Micro Devices, Inc.Inventors: Roden R. Topacio, Neil McLellan, Yip Seng Low, Andrew K W Leung