Abstract: A mask read-only memory (M-ROM) device is provided. In an M-ROM device, a first layer having a first type doping is formed in a substrate. A plurality of buried lines is formed in the first layer of the substrate. The plurality of buried lines are arranged in parallel in a first direction and isolated from each other. An epitaxial growth process is used to form a second layer on the first layer of the substrate. A plurality of diodes is formed in the second layer. The plurality of diodes is arranged in an array. Each diode includes a first electrode having a second type doping and connecting with one of the plurality of buried lines, and a second electrode having a first type doping and located on the first electrode.

Abstract: A method for manufacturing a semiconductor device includes providing a substrate, a first conductor, a second conductor, a first dielectric, a second dielectric, and a designated region. The first conductor is positioned between the first dielectric and the substrate. The second conductor is positioned between the second dielectric and the substrate. The first designated region is positioned in the substrate. The method includes providing a conductive material layer, which completely covers the first dielectric and the second dielectric. The method includes partially removing the conductive material layer to form a third conductor and a fourth conductor. The first dielectric is positioned between the third conductor and the first conductor. The fourth conductor directly contacts the designated region. The method includes implementing a memory unit using the first conductor and the third conductor and includes implementing a logic unit using the second conductor and the designated region.

Abstract: A mask read-only memory (M-ROM) device is provided. In an M-ROM device, a first layer having a first type doping is formed in a substrate. A plurality of buried lines is formed in the first layer of the substrate. The plurality of buried lines are arranged in parallel in a first direction and isolated from each other. An epitaxial growth process is used to form a second layer on the first layer of the substrate. A plurality of diodes is formed in the second layer. The plurality of diodes is arranged in an array. Each diode includes a first electrode having a second type doping and connecting with one of the plurality of buried lines, and a second electrode having a first type doping and located on the first electrode.

Abstract: The disclosed subject matter provides a mask read-only memory (M-ROM) device and fabrication method thereof. In an M-ROM device, a first layer having a first type doping is formed in a substrate. A plurality of buried lines is formed in the first layer of the substrate. The plurality of buried lines are arranged in parallel in a first direction and isolated from each other. An epitaxial growth process is used to form a second layer on the first layer of the substrate. A plurality of diodes is formed in the second layer. The plurality of diodes is arranged in an array. Each diode includes a first electrode having a second type doping and connecting with one of the plurality of buried lines, and a second electrode having a first type doping and located on the first electrode.

Abstract: A method for manufacturing a phase-change device may include the following steps: preparing a substrate; preparing a first dielectric layer, which may be positioned on the substrate; preparing a first electrode, which may be positioned in the first dielectric layer; forming a phase-change material layer, which may overlap the first electrode; processing (e.g., etching) the phase-change material layer to form a phase-change member, which may be electrically connected to the first electrode; forming an etch-stop layer, which may overlap and/or cover the phase-change member; forming an intermediary layer, which may be positioned on the etch-stop layer; forming a second dielectric layer, which may be positioned on the intermediary layer; and forming a second electrode, which may extend through the second dielectric layer, the intermediary layer, and the etch-stop layer and may be electrically connected to the phase-change member.

Abstract: A method for manufacturing a phase-change device may include the following steps: preparing a substrate; preparing a first dielectric layer, which may be positioned on the substrate; preparing a first electrode, which may be positioned in the first dielectric layer; forming a phase-change material layer, which may overlap the first electrode; processing (e.g., etching) the phase-change material layer to form a phase-change member, which may be electrically connected to the first electrode; forming an etch-stop layer, which may overlap and/or cover the phase-change member; forming an intermediary layer, which may be positioned on the etch-stop layer; forming a second dielectric layer, which may be positioned on the intermediary layer; and forming a second electrode, which may extend through the second dielectric layer, the intermediary layer, and the etch-stop layer and may be electrically connected to the phase-change member.

Abstract: A method for setting voltages in a flash memory for high temperature operating life (HTOL) testing is provided. The flash memory includes a substrate, a source, and a control gate. The method includes adjusting the voltages that are applied to the source, the control gate, and the substrate, such that there is no voltage difference between the control gate and the source, and no voltage difference between the control gate and the substrate. Specifically, adjusting the voltages includes setting the voltage that is applied to the source to a ground voltage, setting the voltage that is applied to the control gate to the ground voltage, and setting the voltage that is applied to the substrate to a power supply voltage.

Abstract: A method for manufacturing a phase-change device may include the following steps: preparing a substrate; preparing a first dielectric layer, which may be positioned on the substrate; preparing a first electrode, which may be positioned in the first dielectric layer; forming a phase-change material layer, which may overlap the first electrode; processing (e.g., etching) the phase-change material layer to form a phase-change member, which may be electrically connected to the first electrode; forming an etch-stop layer, which may overlap and/or cover the phase-change member; forming an intermediary layer, which may be positioned on the etch-stop layer; forming a second dielectric layer, which may be positioned on the intermediary layer; and forming a second electrode, which may extend through the second dielectric layer, the intermediary layer, and the etch-stop layer and may be electrically connected to the phase-change member.

Abstract: The disclosed subject matter provides a mask read-only memory (M-ROM) device and fabrication method thereof. In an M-ROM device, a first layer having a first type doping is formed in a substrate. A plurality of buried lines is formed in the first layer of the substrate. The plurality of buried lines are arranged in parallel in a first direction and isolated from each other. An epitaxial growth process is used to form a second layer on the first layer of the substrate. A plurality of diodes is formed in the second layer. The plurality of diodes is arranged in an array. Each diode includes a first electrode having a second type doping and connecting with one of the plurality of buried lines, and a second electrode having a first type doping and located on the first electrode.

Abstract: A method for manufacturing a semiconductor device includes providing a substrate, a first conductor, a second conductor, a first dielectric, a second dielectric, and a designated region. The first conductor is positioned between the first dielectric and the substrate. The second conductor is positioned between the second dielectric and the substrate. The first designated region is positioned in the substrate. The method includes providing a conductive material layer, which completely covers the first dielectric and the second dielectric. The method includes partially removing the conductive material layer to form a third conductor and a fourth conductor. The first dielectric is positioned between the third conductor and the first conductor. The fourth conductor directly contacts the designated region. The method includes implementing a memory unit using the first conductor and the third conductor and includes implementing a logic unit using the second conductor and the designated region.

Abstract: A method for manufacturing a phase-change device may include the following steps: preparing a substrate; preparing a first dielectric layer, which may be positioned on the substrate; preparing a first electrode, which may be positioned in the first dielectric layer; forming a phase-change material layer, which may overlap the first electrode; processing (e.g., etching) the phase-change material layer to form a phase-change member, which may be electrically connected to the first electrode; forming an etch-stop layer, which may overlap and/or cover the phase-change member; forming an intermediary layer, which may be positioned on the etch-stop layer; forming a second dielectric layer, which may be positioned on the intermediary layer; and forming a second electrode, which may extend through the second dielectric layer, the intermediary layer, and the etch-stop layer and may be electrically connected to the phase-change member.

Abstract: A method for setting voltages in a flash memory for high temperature operating life (HTOL) testing is provided. The flash memory includes a substrate, a source, and a control gate. The method includes adjusting the voltages that are applied to the source, the control gate, and the substrate, such that there is no voltage difference between the control gate and the source, and no voltage difference between the control gate and the substrate. Specifically, adjusting the voltages includes setting the voltage that is applied to the source to a ground voltage, setting the voltage that is applied to the control gate to the ground voltage, and setting the voltage that is applied to the substrate to a power supply voltage.

Abstract: A structure and a manufacturing method for an OTP-EPROM in an embedded EEPROM integrated circuit structure. The structure has a substrate that includes a surface region. The structure has a gate dielectric is overlying the surface region. The structure also a first OTP-EPROM gate overlying the gate dielectric layer in a first cell region, and an EEPROM floating gate and a select gate overlying the gate dielectric layer in a second cell region. An insulating layer is overlying the first OTP-EPROM gate, the EEPROM floating gate and the select gate. An OTP-EPROM control gate is overlying the insulating layer and coupled to the first OTP-EPROM gate. An EEPROM control gate is overlying the insulating layer and coupled to the EEPROM floating gate.

Abstract: A structure and a manufacturing method for an OTP-EPROM in an embedded EEPROM integrated circuit structure. The structure has a substrate that includes a surface region. The structure has a gate dielectric is overlying the surface region. The structure also a first OTP-EPROM gate overlying the gate dielectric layer in a first cell region, and an EEPROM floating gate and a select gate overlying the gate dielectric layer in a second cell region. An insulating layer is overlying the first OTP-EPROM gate, the EEPROM floating gate and the select gate. An OTP-EPROM control gate is overlying the insulating layer and coupled to the first OTP-EPROM gate. An EEPROM control gate is overlying the insulating layer and coupled to the EEPROM floating gate.