Patents by Inventor Yi-Peng Jan

Yi-Peng Jan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6274430
    Abstract: A fabrication method for a high voltage electrically erasable read only memory is described, wherein a substrate comprising a memory device region and a peripheral high voltage circuit region is provided. A floating gate is formed on the substrate in the device region, while a gate electrode is formed on the substrate in the peripheral circuit region. Thereafter, an oxide/nitride/oxide layer is formed on the substrate, wherein the oxide/nitride/oxide layer is formed by stacking from bottom to top a first oxide layer, a nitride layer and a second oxide layer. The second oxide layer in the peripheral high voltage circuit region is then removed, followed by removing the nitride layer in the peripheral high voltage circuit region. An oxidation on the second oxide layer and a double diffused drain implantation are conducted to form a bird's beak structure at the bottom corner of the gate electrode and to form a double diffused drain structure in the substrate on both sides of the gate electrode.
    Type: Grant
    Filed: July 26, 2000
    Date of Patent: August 14, 2001
    Assignee: United Microelectronics Corp.
    Inventors: Yi-Peng Jan, Sung-Mu Hsu
  • Patent number: 6197637
    Abstract: A method for fabricating a non-volatile memory cell for a substrate includes the following steps: forming an isolation structure to define an active region on the substrate; forming a channel oxide layer on the active region; forming a conducting layer and a silicon nitride layer over the substrate; defining the polysilicon layer and the silicon nitride layer to form a floating gate on the active region and to form an opening exposing a portion of the isolation structure; conformally forming an etching protection layer which extends from the isolation structure inside the opening up to the silicon nitride layer; forming an oxide layer over the substrate; planarizing the oxide layer to the surface of the silicon nitride layer so that the remainder of the oxide layer is left within the opening; removing the silicon nitride layer; forming conducting spacers on the sidewalls of the remainder of the oxide layer; removing the remainder of the TEOS oxide layer; conformally forming an ONO layer; forming a controlling
    Type: Grant
    Filed: May 30, 2000
    Date of Patent: March 6, 2001
    Assignee: United Microelectronics Corp.
    Inventors: Sung-Mu Hsu, Yi-Peng Jan